?? 220model.vhd
字號:
ALOAD : in std_logic := '0';
ASET : in std_logic := '0';
ACLR : in std_logic := '0';
CIN : in std_logic := '0';
COUT : out std_logic := '0';
--EQ : out std_logic_vector(15 downto 0);
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_COUNTER;
architecture LPM_SYN of LPM_COUNTER is
signal COUNT : std_logic_vector(LPM_WIDTH-1 downto 0);
signal INIT : std_logic := '0';
begin
Counter: process (CLOCK, ACLR, ASET, ALOAD, DATA, INIT)
variable IAVALUE, ISVALUE : integer;
variable IMODULUS : integer;
variable dir_tmp : integer;
begin
-- INITIALIZE TO PVALUE --
if INIT = '0' then
if LPM_PVALUE /= "UNUSED" then
COUNT <= conv_std_logic_vector(str_to_int(LPM_PVALUE), LPM_WIDTH);
else
COUNT <= (OTHERS => '0');
end if;
INIT <= '1';
else
-- SETUP VARIABLES --
IAVALUE := str_to_int(LPM_AVALUE);
ISVALUE := str_to_int(LPM_SVALUE);
if LPM_MODULUS = 0 then
IMODULUS := 2 ** LPM_WIDTH;
else
IMODULUS := LPM_MODULUS;
end if;
if ACLR = '1' then
COUNT <= (OTHERS => '0');
elsif ASET = '1' then
if LPM_AVALUE = "UNUSED" then
COUNT <= (OTHERS => '1');
else
COUNT <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
end if;
elsif ALOAD = '1' then
COUNT <= DATA;
elsif CLOCK'event and CLOCK = '1' then
if CLK_EN = '1' then
if SCLR = '1' then
COUNT <= (OTHERS => '0');
elsif SSET = '1' then
if LPM_SVALUE = "UNUSED" then
COUNT <= (OTHERS => '1');
else
COUNT <= conv_std_logic_vector(ISVALUE, LPM_WIDTH);
end if;
elsif SLOAD = '1' then
COUNT <= DATA;
elsif CNT_EN = '1' then
if LPM_DIRECTION = "UNUSED" then
if UPDOWN = '0' then
dir_tmp := 0; -- decrease
else
dir_tmp := 1; -- increase
end if;
elsif LPM_DIRECTION = "UP" then
dir_tmp := 1; -- increase
elsif LPM_DIRECTION = "DOWN" then
dir_tmp := 0; -- decrease
else
dir_tmp := 1; -- Anything other than legal values.
end if;
if dir_tmp = 1 then
-- INCREMENT --
if COUNT + 1 >= IMODULUS then
COUNT <= conv_std_logic_vector(CIN, LPM_WIDTH);
elsif COUNT + 2 >= IMODULUS then
if CIN = '1' then
COUNT <= conv_std_logic_vector(0, LPM_WIDTH);
else
COUNT <= conv_std_logic_vector(IMODULUS-1, LPM_WIDTH);
end if;
else
COUNT <= COUNT + 1 + CIN;
end if;
else
-- DECREMENT --
if COUNT = 0 then
if CIN = '1' then
COUNT <= conv_std_logic_vector(IMODULUS-2, LPM_WIDTH);
else
COUNT <= conv_std_logic_vector(IMODULUS-1, LPM_WIDTH);
end if;
elsif COUNT = 1 then
if CIN = '1' then
COUNT <= conv_std_logic_vector(IMODULUS-1, LPM_WIDTH);
else
COUNT <= conv_std_logic_vector(0, LPM_WIDTH);
end if;
else
COUNT <= COUNT - 1 - CIN;
end if;
end if;
end if;
end if;
end if;
end if;
end process Counter;
--Decode: process (COUNT)
--variable IMODULUS : integer;
--begin
-- EQ <= (OTHERS => '0');
-- if LPM_MODULUS = 0 then
-- IMODULUS := 2 ** LPM_WIDTH;
-- else
-- IMODULUS := LPM_MODULUS;
-- end if;
--
-- if COUNT = IMODULUS - 1 then
-- EQ(0) <= '1';
-- end if;
--end process Decode;
CarryOut: process (COUNT, CIN)
variable IMODULUS : integer;
variable dir_tmp : integer;
begin
if INIT = '1' then
-- SETUP VARIABLES --
if LPM_MODULUS = 0 then
IMODULUS := 2 ** LPM_WIDTH;
else
IMODULUS := LPM_MODULUS;
end if;
if LPM_DIRECTION = "UNUSED" then
if UPDOWN = '0' then
dir_tmp := 0; -- decrease
else
dir_tmp := 1; -- increase
end if;
elsif LPM_DIRECTION = "UP" then
dir_tmp := 1; -- increase
elsif LPM_DIRECTION = "DOWN" then
dir_tmp := 0; -- decrease
else
dir_tmp := 1; -- Anything other than legal values.
end if;
COUT <= '0';
if CIN = '1' then
if (dir_tmp = 1 and COUNT >= IMODULUS - 2)
or (dir_tmp = 0 and COUNT <= 1) then
COUT <= '1';
end if;
else
if (dir_tmp = 1 and COUNT >= IMODULUS - 1)
or (dir_tmp = 0 and COUNT = 0) then
COUT <= '1';
end if;
end if;
end if;
end process CarryOut;
Q <= COUNT;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
entity LPM_LATCH is
generic (LPM_WIDTH : positive;
LPM_AVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_TYPE: string := "LPM_LATCH";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
GATE : in std_logic;
ASET : in std_logic := '0';
ACLR : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_LATCH;
architecture LPM_SYN of LPM_LATCH is
begin
process (DATA, GATE, ACLR, ASET)
variable IAVALUE : integer;
begin
if ACLR = '1' then
Q <= (OTHERS => '0');
elsif ASET = '1' then
if LPM_AVALUE = "UNUSED" then
Q <= (OTHERS => '1');
else
IAVALUE := str_to_int(LPM_AVALUE);
Q <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
end if;
elsif GATE = '1' then
Q <= DATA;
end if;
end process;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
entity LPM_FF is
generic (LPM_WIDTH : positive;
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_FFTYPE: string := "DFF";
LPM_TYPE: string := "LPM_FF";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SLOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ALOAD : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end LPM_FF;
architecture LPM_SYN of LPM_FF is
signal IQ : std_logic_vector(LPM_WIDTH-1 downto 0);
begin
process (DATA, CLOCK, ACLR, ASET, ALOAD)
variable IAVALUE, ISVALUE : integer;
begin
if ACLR = '1' then
IQ <= (OTHERS => '0');
elsif ASET = '1' then
if LPM_AVALUE = "UNUSED" then
IQ <= (OTHERS => '1');
else
IAVALUE := str_to_int(LPM_AVALUE);
IQ <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
end if;
elsif ALOAD = '1' then
if LPM_FFTYPE = "TFF" then
IQ <= DATA;
end if;
elsif CLOCK'event and CLOCK = '1' then
if ENABLE = '1' then
if SCLR = '1' then
IQ <= (OTHERS => '0');
elsif SSET = '1' then
if LPM_SVALUE = "UNUSED" then
IQ <= (OTHERS => '1');
else
ISVALUE := str_to_int(LPM_SVALUE);
IQ <= conv_std_logic_vector(ISVALUE, LPM_WIDTH);
end if;
elsif SLOAD = '1' then
if LPM_FFTYPE = "TFF" then
IQ <= DATA;
end if;
else
if LPM_FFTYPE = "TFF" then
for i in 0 to LPM_WIDTH-1 loop
if DATA(i) = '1' then
IQ(i) <= not IQ(i);
end if;
end loop;
else
IQ <= DATA;
end if;
end if;
end if;
end if;
end process;
Q <= IQ;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
entity LPM_SHIFTREG is
generic (LPM_WIDTH : positive;
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_DIRECTION: string := "UNUSED";
LPM_TYPE: string := "L_SHIFTREG";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '0');
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SHIFTIN : in std_logic := '1';
LOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
SHIFTOUT : out std_logic);
end LPM_SHIFTREG;
architecture LPM_SYN of LPM_SHIFTREG is
signal IQ : std_logic_vector(LPM_WIDTH downto 0);
begin
process (CLOCK, ACLR, ASET, SCLR)
variable IAVALUE, ISVALUE : integer;
begin
if ACLR = '1' then
IQ <= (OTHERS => '0');
elsif ASET = '1' then
if LPM_AVALUE = "UNUSED" then
IQ <= (OTHERS => '1');
else
IAVALUE := str_to_int(LPM_AVALUE);
IQ <= conv_std_logic_vector(IAVALUE, LPM_WIDTH);
end if;
elsif CLOCK'event and CLOCK = '1' then
if ENABLE = '1' then
if SCLR = '1' then
IQ <= (OTHERS => '0');
elsif SSET = '1' then
if LPM_SVALUE = "UNUSED" then
IQ <= (OTHERS => '1');
else
ISVALUE := str_to_int(LPM_SVALUE);
IQ <= conv_std_logic_vector(ISVALUE, LPM_WIDTH);
end if;
elsif LOAD = '0' then
IQ <= (IQ(LPM_WIDTH-1 downto 0) & SHIFTIN);
else
IQ(LPM_WIDTH-1 downto 0) <= DATA;
end if;
end if;
end if;
end process;
Q <= IQ(LPM_WIDTH-1 downto 0);
SHIFTOUT <= IQ(LPM_WIDTH);
end LPM_SYN;
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use std.textio.all;
use work.LPM_COMPONENTS.all;
entity LPM_RAM_DQ is
generic (LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := L_RAM_DQ;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0 ) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' =>
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