?? m68ksys.h
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/******************************************************************************
(c) Copyright Motorola Semiconductors Hong Kong Limited 1995-2000
ALL RIGHTS RESERVED
******************************************************************************
Project Name : Personal Portable System Manager, PPSM
Project No. : PDAPSM031
Title : M68328ADS hardware location header file
File Name : M68KSYS.H
Created On : 03/28/95
Modifications : 02/02/00 EC - What used to be EZ only is now common
to VZ also (VZ-008)
02/07/00 EC - Added logic to support configurable
interrupt (VZ-011)
02/07/00 EC - Added logic to support new modules (VZ-013)
Release : 02/29/00 PPSM v3.20
Description :
Address locations that are assigned for the M68KPBDS hardware platform.
*****************************************************************************/
#ifndef M68KSYS_INCLUDED
#define M68KSYS_INCLUDED
/* For PPSM, the upper 5 bits of the Interrupt Vector Register (IVR)
is set to 0x40 for the interrupts. This points to
user interrupt vector 64 - address 0x100
Level 1 0x104 vector number = 0x41
Level 2 0x108 vector number = 0x42
Level 3 0x10C vector number = 0x43
Level 4 0x110 vector number = 0x44
Level 5 0x114 vector number = 0x45
Level 6 0x118 vector number = 0x46
Level 7 0x11C vector number = 0x47
*/
/* Modified code and comments for DragonBall EZ */
#define IRPT_VECTOR 0x40
#define NMI_IRPT_ADDR 0x11C /* Interrupt Level 7 */
#define LEVEL_6_IRPT_ADDR 0x118 /* Interrupt Level 6 */
#define PEN_IRPT_ADDR 0x114 /* Interrupt Level 5 */
#define LEVEL_4_IRPT_ADDR 0x110 /* Interrupt Level 4 */
#define IRQ3_IRPT_ADDR 0x10C /* Interrupt Level 3 */
#define IRQ2_IRPT_ADDR 0x108 /* Interrupt Level 2 */
#define IRQ1_IRPT_ADDR 0x104 /* Interrupt Level 1 */
#if defined(EZ328) || defined(VZ328) /*** MOD VZ-008 ***/
#define INTERNAL_IRPT_ADDR 0x2C /* Internal - using F-Line interrupt */
/* default on : NMI (23), MIRQ5 (20), RTC (4), TMR (1) */
#if defined(EZ328)
#define IMR_DEFAULT 0x006FFFED
#elif defined(VZ328)
#define IMR_DEFAULT 0x016FFFED /*** MOD VZ-013 ***/
#endif
#define M328_TMR1_BIT 0x00000002 /* modified */
#define M328_TMR1_MASK 0x00FFFFFD /* modified */
#define M328_SAM_BIT 0x00400000 /* new in EZ*/
#define M328_SAM_MASK 0x00BFFFFF /* new in EZ*/
#define IRPT6_SAM 0x00400000 /* SAM */
#define IRPT6_TIMER1 0x00000002 /* bit 1 */
#define IRPT4_INT 0x00000F00 /* bit 8 to 11 modified */
#define IRPT4_SAM 0x00400000 /* bit 22 */
/* M68EZ328 SAM */
#define SAM3_ENABLE 0x0800
#define SAM3_DISABLE 0xF7FF
/* New definition for EZ - Interrupt Wakeup Register */
#define IMR_MASK 0x00A00069 /* PEN, RTC, IRQx and INTx, SAM, UART, PWM */
#if defined(EZ328) /*** MOD VZ-008 ***/
#if defined(MHZ16)
#define PLL_DEFAULT 0x2400 /* PLL default modified */
#elif defined(MHZ20)
#define PLL_DEFAULT 0x2400
#else
#error /* Undefined compile flag - frequency */
#endif
#elif defined(VZ328)
#if defined(MHZ33)
#define PLL_DEFAULT 0x2400
#elif defined(MHZ16)
#define PLL_DEFAULT 0x2420
#else
#error /* Undefined compile flag - frequency */
#endif
#else
#error /* Undefined compile flag - platform */
#endif
#define DMACLK_MASK 0xFF1F /* DMACLK maks - new */
#else /*** MOD VZ-008 ***/
#error /* Undefined compile flag - platform */
#define INTERNAL_IRPT_ADDR 0x28 /* Internal - using F-Line interrupt */
/* default on : NMI (23), TMR1 (22), PEN (20), IRQx, INTx,
RTC (4), WatchDog (3), UART (2), TMR2 (1) */
#define IMR_DEFAULT 0x002FFFE1
#define M328_TMR1_BIT 0x00400000
#define M328_TMR1_MASK 0x00BFFFFF
#define IRPT6_SPIS 0x00200000 /* bit 21 */
#define IRPT6_TIMER1 0x00400000 /* bit 22 */
#define IRPT4_TIMER2 0x00000002 /* bit 1 */
#define IRPT4_LCDC 0x00000020 /* bit 5 */
#define IRPT4_INT 0x0000FF00 /* bit 8 to bit 15 */
/* M68328 SPI Slave default values */
#define SPI_START 0x430F /* Divide clock by 4, 16 bits */
#define SPI_STOP 0x420F
#define XCH_BIT 0x0100
/* Interrupt Wakeup Register */
#define IWR_DEFAULT 0x001FFF94 /* PEN, RTC, IRQx and INTx, UART, PWM */
#define PLL_DEFAULT 0x2710 /* PLL default */
#endif
#define M328_UART_MASK 0x00FFFFFB
#define M328_PEN_BIT 0x00100000 /* bit 20 */
#define M328_PEN_MASK 0x00EFFFFF /* bit 20 */
#define IRPT_LEVEL_6 6
#define IRPT_LEVEL_5 5 /*** ADD VZ-011 ***/
#define IRPT_LEVEL_4 4
#define IRPT_LEVEL_3 3 /*** ADD VZ-011 ***/
#define IRPT_LEVEL_2 2 /*** ADD VZ-011 ***/
#define IRPT_LEVEL_1 1 /*** ADD VZ-011 ***/
/* Level 6 interrupts */
#define IRPT6_IRQ6 0x00080000 /* bit 19 */
/* Level 4 interrupts */
#define IRPT4_SPIM 0x00000001 /* bit 0 */
#define IRPT4_UART 0x00000004 /* bit 2 */
#define IRPT4_WATCHDOG 0x00000008 /* bit 3 */
#define IRPT4_RTC 0x00000010 /* bit 4 */
#define IRPT4_KEY 0x00000040 /* bit 6 */
#define IRPT4_PWM 0x00000080 /* bit 7 */
/*** ADD VZ-011 ... ***/
#if defined(VZ328)
/* Interrupt status, masking, and pending bit positions for the new VZ modules */
#define IRPTX_UART2 0x00001000 /* bit 12 */
#define IRPTX_PWM2 0x00002000 /* bit 13 */
#define IRPTX_SPI1 0x00200000 /* bit 21 */
#define IRPTX_TMR2 0x01000000 /* bit 24 */
/* User-configurable interrupt modules */
#define IRPT_MODULE_TMR2 0
#define IRPT_MODULE_PWM2 1
#define IRPT_MODULE_UART2 2
#define IRPT_MODULE_SPI1 3
#endif
/*** ... ADD VZ-011 ***/
/* M68328 timer */
#define TMR_DEFAULT 0x0008 /* take source from 32.768KHz */
#define TMR_STOP_MASK 0xFFFE
#define TMR_START_MASK 0x0011
/* M68328 RTC */
#define M328RTC_ALARM 0x0004 /* bit 2 */
#define M328RTC_MID 0x0008 /* bit 3 */
#if defined(EZ328) || defined(VZ328) /*** MOD VZ-008 ***/
#define M328RTC_PERIOD 0x0032 /* bit 1, 4 and 5 */
#else
#error /* Undefined compile flag - platform */
#define M328RTC_PERIOD 0x0012 /* bit1 and 4 */
#endif
#define M328RTC_PER_SEC 0x0010 /* bit 4 */
#define M328RTC_PER_MIN 0x0002 /* bit 1 */
/************************************************************************
For Power Management
************************************************************************/
/* Power Control Modeule */
#define PCM_DEFAULT 0x001F /* Power Control Module */
#define POWER_ENABLE 0x0080 /* bit 7 = 1 */
#define POWER_DISABLE 0x007F /* bit 7 = 0 */
#define CPU_STOP 0x0040 /* bit 6 = 1 */
#define CPU_NORMAL 0x00BF /* bit 6 = 0 */
#define DUTY_MASK 0x00E0 /* bit 0 to 4 */
/* Phase Locked Loop */
#define SYSCLK_MASK 0xF8FF /* SYSCLK mask */
#define PLL_DISABLE 0x0008 /* bit 3 = 1 */
/* LCDC ON and Off */
#define LCDC_MASK 0x7F /* bit 7 modified */
#define LCDC_BIT 0x80 /* bit 7 */
#define DRAMC_SELFREFRESH 0x4000 /* bit 14 = 1 */
/* M68328 registers */
#include "m68328.h"
#endif
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