//
//				SANTAK 3A3
//
//###########################################################################
//
// FILE:	DSP2810_Device.h
//
// TITLE:	TMS320F2810 registers define
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who  | Description of changes
// .00 | 17  07 2003 | lg   |
//
//###########################################################################
//---------------------------------------------------------------------------
// Used for calculating delays in micro-seconds:
//

#define CPU_CLOCK_SPEED      6.6667L   // for a 150MHz CPU clock speed
#define DELAY_US(A)  DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_CLOCK_SPEED) - 9.0L) / 5.0L)

//---------------------------------------------------------------------------
// Common CPU Definitions:
//

extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
#define  EINT   asm(" clrc INTM")
#define  DINT   asm(" setc INTM")
#define  ERTM   asm(" clrc DBGM")
#define  DRTM   asm(" setc DBGM")
#define	 EALLOW	asm(" EALLOW")
#define	 EDIS	asm(" EDIS")
#define  ESTOP0 asm(" ESTOP0")

#define	M_INT1		0x0001
#define	M_INT2		0x0002
#define	M_INT3		0x0004
#define	M_INT4		0x0008
#define	M_INT5		0x0010
#define	M_INT6		0x0020
#define	M_INT7		0x0040
#define	M_INT8		0x0080
#define	M_INT9		0x0100
#define	M_INT10		0x0200
#define	M_INT11		0x0400
#define	M_INT12		0x0800
#define	M_INT13		0x1000
#define	M_INT14		0x2000
#define	M_DLOG		0x4000
#define	M_RTOS		0x8000

#define	BIT0		0x0001
#define	BIT1		0x0002
#define	BIT2		0x0004
#define	BIT3		0x0008
#define	BIT4		0x0010
#define	BIT5		0x0020
#define	BIT6		0x0040
#define	BIT7		0x0080
#define	BIT8		0x0100
#define	BIT9		0x0200
#define	BIT10		0x0400
#define	BIT11		0x0800
#define	BIT12		0x1000
#define	BIT13		0x2000
#define	BIT14		0x4000
#define	BIT15		0x8000



//---------------------------------------------------------------------------
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//

//---------------------------------------------------------------------------
// ADC Individual Register Bit Definitions:

/*
INDEX:    ADC_Registers ()
*/
struct ADCTRL1_BITS {     // bits  description
    unsigned int  rsvd1:4;      // 3:0   reserved
    unsigned int  SEQ_CASC:1;   // 4     Cascaded sequencer mode
    unsigned int  rsvd2:1;      // 5     reserved
    unsigned int  CONT_RUN:1;   // 6     Continuous run
    unsigned int  CPS:1;        // 7     ADC core clock prescaler
    unsigned int  ACQ_PS:4;     // 11:8  Acquisition window size
    unsigned int  SUSMOD:2;     // 13:12 Emulation suspend mode
    unsigned int  RESET:1;      // 14    ADC reset
    unsigned int  rsvd3:1;      // 15    reserved
};


union ADCTRL1_REG {
   unsigned int             all;
   struct ADCTRL1_BITS  bit;
};


struct ADCTRL2_BITS {        // bits  description
    unsigned int  EVB_SOC_SEQ2:1;   // 0    Event manager B SOC mask for SEQ2
    unsigned int  rsvd1:1;          // 1    reserved
    unsigned int  INT_MOD_SEQ2:1;   // 2    SEQ2 Interrupt mode
    unsigned int  INT_ENA_SEQ2:1;   // 3    SEQ2 Interrupt enable
    unsigned int  rsvd2:1;          // 4    reserved
    unsigned int  SOC_SEQ2:1;       // 5    Start of conversion for SEQ2
    unsigned int  RST_SEQ2:1;       // 6    Reset SEQ2
    unsigned int  EXT_SOC_SEQ1:1;   // 7    External start of conversion for SEQ1
    unsigned int  EVA_SOC_SEQ1:1;   // 8    Event manager A SOC mask for SEQ1
    unsigned int  rsvd3:1;          // 9    reserved
    unsigned int  INT_MOD_SEQ1:1;   // 10   SEQ1 Interrupt mode
    unsigned int  INT_ENA_SEQ1:1;   // 11   SEQ1 Interrupt enable
    unsigned int  rsvd4:1;          // 12   reserved
    unsigned int  SOC_SEQ1:1;       // 13   Start of conversion trigger for SEQ1
    unsigned int  RST_SEQ1:1;       // 14   Restart sequencer 1   
    unsigned int  EVB_SOC_SEQ:1;    // 15   EVB SOC enable
};


union ADCTRL2_REG {
   unsigned int             all;
   struct ADCTRL2_BITS  bit;
};


struct ADCCASEQSR_BITS {  // bits  description
    unsigned int  SEQ1_STATE:4;     // 3:0    SEQ1 state
    unsigned int  SEQ2_STATE:3;     // 6:2    SEQ2 state
    unsigned int  rsvd1:1;          // 7      resverved
    unsigned int  SEQ_CNTR:4;       // 11:8   Sequencing counter status 
    unsigned int  rsvd2:4;          // 15:12  reserved  
};

union ADCCASEQSR_REG {
   unsigned int             all;
   struct ADCCASEQSR_BITS bit;
};


struct ADCMAXCONV_BITS {
    unsigned int  MAX_CONV:7;          // 6:0   Max number of conversions
    unsigned int  rsvd1:9;             // 15:7  reserved 
};

union ADCMAXCONV_REG {
   unsigned int             all;
   struct ADCMAXCONV_BITS  bit;
};


struct ADCCHSELSEQ1_BITS {
    unsigned int  CONV00:4;
    unsigned int  CONV01:4;
    unsigned int  CONV02:4;
    unsigned int  CONV03:4;
};

union  ADCCHSELSEQ1_REG{
   unsigned int             all;
   struct ADCCHSELSEQ1_BITS  bit;
};

struct ADCCHSELSEQ2_BITS {
    unsigned int  CONV04:4;
    unsigned int  CONV05:4;
    unsigned int  CONV06:4;
    unsigned int  CONV07:4;
};

union  ADCCHSELSEQ2_REG{
   unsigned int             all;
   struct ADCCHSELSEQ2_BITS  bit;
};

struct ADCCHSELSEQ3_BITS {
    unsigned int  CONV08:4;
    unsigned int  CONV09:4;
    unsigned int  CONV10:4;
    unsigned int  CONV11:4;
};

union  ADCCHSELSEQ3_REG{
   unsigned int             all;
   struct ADCCHSELSEQ3_BITS  bit;
};

struct ADCCHSELSEQ4_BITS {
    unsigned int  CONV12:4;
    unsigned int  CONV13:4;
    unsigned int  CONV14:4;
    unsigned int  CONV15:4;
};

union  ADCCHSELSEQ4_REG {
   unsigned int             all;
   struct ADCCHSELSEQ4_BITS  bit;
};

struct ADCTRL3_BITS {
    unsigned int   SMODE_SEL:1;          // 0     Sampling mode select
    unsigned int   ADCCLKPS:4;           // 4:1   ADC core clock divider
    unsigned int   ADCPWDN:1;            // 5     ADC powerdown
    unsigned int   ADCBGRFDN:2;          // 7:6   ADC bandgap/ref power down
    unsigned int   rsvd1:8;              // 15:8 reserved
}; 

union  ADCTRL3_REG {
   unsigned int             all;
   struct ADCTRL3_BITS  bit;
};


struct ADCST_BITS {
    unsigned int   INT_SEQ1:1;            // 0  SEQ1 Interrupt flag  
    unsigned int   INT_SEQ2:1;            // 1  SEQ2 Interrupt flag
    unsigned int   SEQ1_BSY:1;            // 2  SEQ1 busy status
    unsigned int   SEQ2_BSY:1;            // 3  SEQ2 busy status
    unsigned int   INT_SEQ1_CLR:1;        // 4  SEQ1 Interrupt clear
    unsigned int   INT_SEQ2_CLR:1;        // 5  SEQ2 Interrupt clear
    unsigned int   EOS_BUF1:1;            // 6  End of sequence buffer1
    unsigned int   EOS_BUF2:1;            // 7  End of sequence buffer2
    unsigned int   rsvd1:8;               // 15:8
};


union  ADCST_REG {
   unsigned int             all;
   struct ADCST_BITS  bit;
};


struct ADC_REGS {
    union ADCTRL1_REG ADCTRL1;          // ADC Control 1
    union ADCTRL2_REG ADCTRL2;          // ADC Control 2
    union ADCMAXCONV_REG ADCMAXCONV;       // Max conversions
    union ADCCHSELSEQ1_REG ADCCHSELSEQ1;   // Channel select sequencing control
    union ADCCHSELSEQ2_REG ADCCHSELSEQ2;
    union ADCCHSELSEQ3_REG ADCCHSELSEQ3;
    union ADCCHSELSEQ4_REG ADCCHSELSEQ4;
    union ADCCASEQSR_REG ADCASEQSR;    // Autosequence status register
    unsigned int ADCRESULT0;                  // Conversion Result Buffer 0 - 15
    unsigned int ADCRESULT1;
    unsigned int ADCRESULT2;
    unsigned int ADCRESULT3;
    unsigned int ADCRESULT4;
    unsigned int ADCRESULT5;
    unsigned int ADCRESULT6;
    unsigned int ADCRESULT7;
    unsigned int ADCRESULT8;
    unsigned int ADCRESULT9;
    unsigned int ADCRESULT10;
    unsigned int ADCRESULT11;
    unsigned int ADCRESULT12;
    unsigned int ADCRESULT13;
    unsigned int ADCRESULT14;
    unsigned int ADCRESULT15;
    union ADCTRL3_REG ADCTRL3;         // ADC Contrl 3  
    union ADCST_REG ADCST;             // ADC Status Register
};
// ADC registers define End

//---------------------------------------------------------------------------
// CPU Timer Register Bit Definitions:
//
//
// TCR: Control register bit definitions:
/*
INDEX:    CPUTimer_Registers ()
*/

struct  TCR_BITS {        // bits  description
   unsigned int    OUTSTS:1;      // 0     Current state of TOUT
   unsigned int    FORCE:1;       // 1     Force TOUT
   unsigned int    POL:1;         // 2     Output polarity
   unsigned int    TOG:1;         // 3     Output toggle mode
   unsigned int    TSS:1;         // 4     Timer Start/Stop
   unsigned int    TRB:1;         // 5     Timer reload
   unsigned int    FRCEN:1;       // 6     Force enable
   unsigned int    PWIDTH:3;      // 9:7   BitTOUT output pulse width
   unsigned int    SOFT:1;        // 10    Emulation modes
   unsigned int    FREE:1;        // 11
   unsigned int    rsvd:2;        // 12:13 reserved
   unsigned int    TIE:1;         // 14    Output enable
   unsigned int    TIF:1;         // 15    Interrupt flag
}; 

union TCR_REG {
   unsigned int             all;
   struct TCR_BITS  bit;
};

// TPR: Pre-scale low bit definitions:
struct  TPR_BITS {        // bits  description
   unsigned int     TDDR:8;       // 7:0   Divide-down low
   unsigned int     PSC:8;        // 15:8  Prescale counter low
};

union TPR_REG {
   unsigned int             all;
   struct TPR_BITS  bit;
};

// TPRH: Pre-scale high bit definitions:
struct  TPRH_BITS {       // bits  description
   unsigned int     TDDRH:8;      // 7:0   Divide-down high
   unsigned int     PSCH:8;       // 15:8  Prescale counter high
};

union TPRH_REG {
   unsigned int             all;
   struct TPRH_BITS bit;
};

// TIM, TIMH: Timer register definitions:
struct TIM_REG {
   unsigned int  LSW;
   unsigned int  MSW;
};

union TIM_GROUP {
   unsigned long            all;
   struct TIM_REG  half;
};