?? registers.h
字號:
unsigned int TCOF1:1; // 16 TSC Overflow flag
unsigned int MTOF1:1; // 17 Mailbox Timeout flag
unsigned int rsvd2:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIF1_REG {
unsigned long all;
struct CANGIF1_BITS bit;
};
/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */
struct CANMIM_BITS { // bit description
unsigned int MIM0:1; // 0 MIM for Mailbox 0
unsigned int MIM1:1; // 1 MIM for Mailbox 1
unsigned int MIM2:1; // 2 MIM for Mailbox 2
unsigned int MIM3:1; // 3 MIM for Mailbox 3
unsigned int MIM4:1; // 4 MIM for Mailbox 4
unsigned int MIM5:1; // 5 MIM for Mailbox 5
unsigned int MIM6:1; // 6 MIM for Mailbox 6
unsigned int MIM7:1; // 7 MIM for Mailbox 7
unsigned int MIM8:1; // 8 MIM for Mailbox 8
unsigned int MIM9:1; // 9 MIM for Mailbox 9
unsigned int MIM10:1; // 10 MIM for Mailbox 10
unsigned int MIM11:1; // 11 MIM for Mailbox 11
unsigned int MIM12:1; // 12 MIM for Mailbox 12
unsigned int MIM13:1; // 13 MIM for Mailbox 13
unsigned int MIM14:1; // 14 MIM for Mailbox 14
unsigned int MIM15:1; // 15 MIM for Mailbox 15
unsigned int MIM16:1; // 16 MIM for Mailbox 16
unsigned int MIM17:1; // 17 MIM for Mailbox 17
unsigned int MIM18:1; // 18 MIM for Mailbox 18
unsigned int MIM19:1; // 19 MIM for Mailbox 19
unsigned int MIM20:1; // 20 MIM for Mailbox 20
unsigned int MIM21:1; // 21 MIM for Mailbox 21
unsigned int MIM22:1; // 22 MIM for Mailbox 22
unsigned int MIM23:1; // 23 MIM for Mailbox 23
unsigned int MIM24:1; // 24 MIM for Mailbox 24
unsigned int MIM25:1; // 25 MIM for Mailbox 25
unsigned int MIM26:1; // 26 MIM for Mailbox 26
unsigned int MIM27:1; // 27 MIM for Mailbox 27
unsigned int MIM28:1; // 28 MIM for Mailbox 28
unsigned int MIM29:1; // 29 MIM for Mailbox 29
unsigned int MIM30:1; // 30 MIM for Mailbox 30
unsigned int MIM31:1; // 31 MIM for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANMIM_REG {
unsigned long all;
struct CANMIM_BITS bit;
};
/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */
struct CANMIL_BITS { // bit description
unsigned int MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6
unsigned int MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6
};
/* Allow access to the bit fields or entire register */
union CANMIL_REG {
unsigned long all;
struct CANMIL_BITS bit;
};
/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */
struct CANOPC_BITS { // bit description
unsigned int OPC0:1; // 0 OPC for Mailbox 0
unsigned int OPC1:1; // 1 OPC for Mailbox 1
unsigned int OPC2:1; // 2 OPC for Mailbox 2
unsigned int OPC3:1; // 3 OPC for Mailbox 3
unsigned int OPC4:1; // 4 OPC for Mailbox 4
unsigned int OPC5:1; // 5 OPC for Mailbox 5
unsigned int OPC6:1; // 6 OPC for Mailbox 6
unsigned int OPC7:1; // 7 OPC for Mailbox 7
unsigned int OPC8:1; // 8 OPC for Mailbox 8
unsigned int OPC9:1; // 9 OPC for Mailbox 9
unsigned int OPC10:1; // 10 OPC for Mailbox 10
unsigned int OPC11:1; // 11 OPC for Mailbox 11
unsigned int OPC12:1; // 12 OPC for Mailbox 12
unsigned int OPC13:1; // 13 OPC for Mailbox 13
unsigned int OPC14:1; // 14 OPC for Mailbox 14
unsigned int OPC15:1; // 15 OPC for Mailbox 15
unsigned int OPC16:1; // 16 OPC for Mailbox 16
unsigned int OPC17:1; // 17 OPC for Mailbox 17
unsigned int OPC18:1; // 18 OPC for Mailbox 18
unsigned int OPC19:1; // 19 OPC for Mailbox 19
unsigned int OPC20:1; // 20 OPC for Mailbox 20
unsigned int OPC21:1; // 21 OPC for Mailbox 21
unsigned int OPC22:1; // 22 OPC for Mailbox 22
unsigned int OPC23:1; // 23 OPC for Mailbox 23
unsigned int OPC24:1; // 24 OPC for Mailbox 24
unsigned int OPC25:1; // 25 OPC for Mailbox 25
unsigned int OPC26:1; // 26 OPC for Mailbox 26
unsigned int OPC27:1; // 27 OPC for Mailbox 27
unsigned int OPC28:1; // 28 OPC for Mailbox 28
unsigned int OPC29:1; // 29 OPC for Mailbox 29
unsigned int OPC30:1; // 30 OPC for Mailbox 30
unsigned int OPC31:1; // 31 OPC for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANOPC_REG {
unsigned long all;
struct CANOPC_BITS bit;
};
/* eCAN TX I/O Control Register (CANTIOC) bit definitions */
struct CANTIOC_BITS { // bits description
unsigned int rsvd1:3; // 2:0 reserved
unsigned int TXFUNC:1; // 3 TXFUNC
unsigned int rsvd2:12; // 15:4 reserved
unsigned int rsvd3:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANTIOC_REG {
unsigned long all;
struct CANTIOC_BITS bit;
};
/* eCAN RX I/O Control Register (CANRIOC) bit definitions */
struct CANRIOC_BITS { // bits description
unsigned int rsvd1:3; // 2:0 reserved
unsigned int RXFUNC:1; // 3 RXFUNC
unsigned int rsvd2:12; // 15:4 reserved
unsigned int rsvd3:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANRIOC_REG {
unsigned long all;
struct CANRIOC_BITS bit;
};
/* eCAN Time-out Control register (CANTOC) bit definitions */
struct CANTOC_BITS { // bit description
unsigned int TOC0:1; // 0 TOC for Mailbox 0
unsigned int TOC1:1; // 1 TOC for Mailbox 1
unsigned int TOC2:1; // 2 TOC for Mailbox 2
unsigned int TOC3:1; // 3 TOC for Mailbox 3
unsigned int TOC4:1; // 4 TOC for Mailbox 4
unsigned int TOC5:1; // 5 TOC for Mailbox 5
unsigned int TOC6:1; // 6 TOC for Mailbox 6
unsigned int TOC7:1; // 7 TOC for Mailbox 7
unsigned int TOC8:1; // 8 TOC for Mailbox 8
unsigned int TOC9:1; // 9 TOC for Mailbox 9
unsigned int TOC10:1; // 10 TOC for Mailbox 10
unsigned int TOC11:1; // 11 TOC for Mailbox 11
unsigned int TOC12:1; // 12 TOC for Mailbox 12
unsigned int TOC13:1; // 13 TOC for Mailbox 13
unsigned int TOC14:1; // 14 TOC for Mailbox 14
unsigned int TOC15:1; // 15 TOC for Mailbox 15
unsigned int TOC16:1; // 16 TOC for Mailbox 16
unsigned int TOC17:1; // 17 TOC for Mailbox 17
unsigned int TOC18:1; // 18 TOC for Mailbox 18
unsigned int TOC19:1; // 19 TOC for Mailbox 19
unsigned int TOC20:1; // 20 TOC for Mailbox 20
unsigned int TOC21:1; // 21 TOC for Mailbox 21
unsigned int TOC22:1; // 22 TOC for Mailbox 22
unsigned int TOC23:1; // 23 TOC for Mailbox 23
unsigned int TOC24:1; // 24 TOC for Mailbox 24
unsigned int TOC25:1; // 25 TOC for Mailbox 25
unsigned int TOC26:1; // 26 TOC for Mailbox 26
unsigned int TOC27:1; // 27 TOC for Mailbox 27
unsigned int TOC28:1; // 28 TOC for Mailbox 28
unsigned int TOC29:1; // 29 TOC for Mailbox 29
unsigned int TOC30:1; // 30 TOC for Mailbox 30
unsigned int TOC31:1; // 31 TOC for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTOC_REG {
unsigned long all;
struct CANTOC_BITS bit;
};
/* eCAN Time-out Status register (CANTOS) bit definitions */
struct CANTOS_BITS { // bit description
unsigned int TOS0:1; // 0 TOS for Mailbox 0
unsigned int TOS1:1; // 1 TOS for Mailbox 1
unsigned int TOS2:1; // 2 TOS for Mailbox 2
unsigned int TOS3:1; // 3 TOS for Mailbox 3
unsigned int TOS4:1; // 4 TOS for Mailbox 4
unsigned int TOS5:1; // 5 TOS for Mailbox 5
unsigned int TOS6:1; // 6 TOS for Mailbox 6
unsigned int TOS7:1; // 7 TOS for Mailbox 7
unsigned int TOS8:1; // 8 TOS for Mailbox 8
unsigned int TOS9:1; // 9 TOS for Mailbox 9
unsigned int TOS10:1; // 10 TOS for Mailbox 10
unsigned int TOS11:1; // 11 TOS for Mailbox 11
unsigned int TOS12:1; // 12 TOS for Mailbox 12
unsigned int TOS13:1; // 13 TOS for Mailbox 13
unsigned int TOS14:1; // 14 TOS for Mailbox 14
unsigned int TOS15:1; // 15 TOS for Mailbox 15
unsigned int TOS16:1; // 16 TOS for Mailbox 16
unsigned int TOS17:1; // 17 TOS for Mailbox 17
unsigned int TOS18:1; // 18 TOS for Mailbox 18
unsigned int TOS19:1; // 19 TOS for Mailbox 19
unsigned int TOS20:1; // 20 TOS for Mailbox 20
unsigned int TOS21:1; // 21 TOS for Mailbox 21
unsigned int TOS22:1; // 22 TOS for Mailbox 22
unsigned int TOS23:1; // 23 TOS for Mailbox 23
unsigned int TOS24:1; // 24 TOS for Mailbox 24
unsigned int TOS25:1; // 25 TOS for Mailbox 25
unsigned int TOS26:1; // 26 TOS for Mailbox 26
unsigned int TOS27:1; // 27 TOS for Mailbox 27
unsigned int TOS28:1; // 28 TOS for Mailbox 28
unsigned int TOS29:1; // 29 TOS for Mailbox 29
unsigned int TOS30:1; // 30 TOS for Mailbox 30
unsigned int TOS31:1; // 31 TOS for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTOS_REG {
unsigned long all;
struct CANTOS_BITS bit;
};
/**************************************/
/* eCAN Control & Status register file */
/**************************************/
struct ECAN_REGS {
union CANME_REG CANME; // Mailbox Enable
union CANMD_REG CANMD; // Mailbox Direction
union CANTRS_REG CANTRS; // Transmit Request Set
union CANTRR_REG CANTRR; // Transmit Request Reset
union CANTA_REG CANTA; // Transmit Acknowledge
union CANAA_REG CANAA; // Abort Acknowledge
union CANRMP_REG CANRMP; // Received Message Pending
union CANRML_REG CANRML; // Received Message Lost
union CANRFP_REG CANRFP; // Remote Frame Pending
union CANGAM_REG CANGAM; // Global Acceptance Mask
union CANMC_REG CANMC; // Master Control
union CANBTC_REG CANBTC; // Bit Timing
union CANES_REG CANES; // Error Status
union CANTEC_REG CANTEC; // Transmit Error Counter
union CANREC_REG CANREC; // Receive Error Counter
union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0
union CANGIM_REG CANGIM; // Global Interrupt Mask 0
union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1
union CANMIM_REG CANMIM; // Mailbox Interrupt Mask
union CANMIL_REG CANMIL; // Mailbox Interrupt Level
union CANOPC_REG CANOPC; // Overwrite Protection Control
union CANTIOC_REG CANTIOC; // TX I/O Control
union CANRIOC_REG CANRIOC; // RX I/O Control
unsigned long CANTSC; // Time-stamp counter
union CANTOC_REG CANTOC; // Time-out Control
union CANTOS_REG CANTOS; // Time-out Status
};
/* --------------------------------------------------- */
/* eCAN Mailbox Registers */
/* ----------------------------------------------------*/
/* eCAN Message ID (MSGID) bit definitions */
struct CANMSGID_BITS { // bits description
unsigned int EXTMSGID_L:16; // 0:15
unsigned int EXTMSGID_H:2; // 16:17
unsigned int STDMSGID:11; // 18:28
unsigned int AAM:1; // 29
unsigned int AME:1; // 30
unsigned int IDE:1; // 31
};
/* Allow access to the bit fields or entire register */
union CANMSGID_REG {
unsigned long all;
struct CANMSGID_BITS bit;
};
/* eCAN Message Control Field (MSGCTRL) bit definitions */
struct CANMSGCTRL_BITS { // bits description
unsigned int DLC:4; // 0:3
unsigned int RTR:1; // 4
unsigned int rsvd1:3; // 7:5 reserved
unsigned int TPL:5; // 12:8
unsigned int rsvd2:3; // 15:13 reserved
unsigned int rsvd3:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANMSGCTRL_REG {
unsigned long all;
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