* This routine uses global variables in the CS_END_DEVICE structure to configure the 
* adapter for the board-specific IO circuitry and media types supported.
*        
* RETURNS: Nothing
*         
*/

LOCAL void sysEnetHWInit( CS_END_DEVICE *pCS )
{
   USHORT BusCtl;
   USHORT SelfCtl;
   IOADDR DataPort;
   IOADDR AddrPort;

   DataPort=pCS->IOAddr + PORT_PKTPG_DATA;
   AddrPort=pCS->IOAddr + PORT_PKTPG_PTR;
   



   /* If memory mode is enabled */
   if ( pCS->ConfigFlags & CFGFLG_MEM_MODE )
   {
      /* If external logic is present for address decoding */
      if ( csReadPacketPage(pCS,PKTPG_SELF_ST) & SELF_ST_EL_PRES )
      {
         /* Program the external logic to decode address bits SA20-SA23 */
         csWritePacketPage( pCS, PKTPG_EEPROM_CMD,
               ((UINT)(pCS->pPacketPage)>>20) | EEPROM_CMD_ELSEL );
      }

      /* Setup chip for memory mode */
      csWritePacketPage( pCS, PKTPG_MEM_BASE, (UINT)(pCS->pPacketPage)&0xFFFF );
      csWritePacketPage( pCS, PKTPG_MEM_BASE+2, (UINT)(pCS->pPacketPage)>>16 );
      BusCtl = BUS_CTL_MEM_MODE;
      if ( pCS->ConfigFlags & CFGFLG_USE_SA )
         BusCtl |= BUS_CTL_USE_SA;
      csWritePacketPage( pCS, PKTPG_BUS_CTL, BusCtl );

      /* We are in memory mode now! */
      pCS->InMemoryMode = TRUE;
   }

   /* If IOCHRDY is enabled then clear the bit in the BusCtl register */
   BusCtl = csReadPacketPage( pCS, PKTPG_BUS_CTL );
   if ( pCS->ConfigFlags & CFGFLG_IOCHRDY )
      csWritePacketPage( pCS, PKTPG_BUS_CTL, BusCtl & ~BUS_CTL_IOCHRDY );
   else
      csWritePacketPage( pCS, PKTPG_BUS_CTL, BusCtl | BUS_CTL_IOCHRDY );

   /* Set the Line Control register to match the media type */
   if ( pCS->MediaType == MEDIA_10BASET )
      csWritePacketPage( pCS, PKTPG_LINE_CTL, LINE_CTL_10BASET );
   else
      csWritePacketPage( pCS, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY );

   /* Set the BSTATUS/HC1 pin to be used as HC1 */
   /* HC1 is used to enable the DC/DC converter */
   SelfCtl = SELF_CTL_HC1E;

   /* If the media type is 10Base2 */
   if ( pCS->MediaType == MEDIA_10BASE2 )
   {
      /* Enable the DC/DC converter */
      /* If the DC/DC converter has a low enable */
      if ( (pCS->ConfigFlags & CFGFLG_DCDC_POL) == 0 )
         /* Set the HCB1 bit, which causes the HC1 pin to go low */
         SelfCtl |= SELF_CTL_HCB1;
   }
   else  /* Media type is 10BaseT or AUI */
   {
      /* Disable the DC/DC converter */
      /* If the DC/DC converter has a high enable */
      if ( (pCS->ConfigFlags & CFGFLG_DCDC_POL) != 0 )
         /* Set the HCB1 bit, which causes the HC1 pin to go low */
         SelfCtl |= SELF_CTL_HCB1;
   }
   csWritePacketPage( pCS, PKTPG_SELF_CTL, SelfCtl );

   /* If media type is 10BaseT */
   if ( pCS->MediaType == MEDIA_10BASET )
   {
      /* If full duplex mode then set the FDX bit in TestCtl register */
      if ( pCS->ConfigFlags & CFGFLG_FDX )
         csWritePacketPage( pCS, PKTPG_TEST_CTL, TEST_CTL_FDX );
   }
 
}



/******************************************************************************
*
* sysEnetIntEnable - enable CS8900 interrupts at the system level
*
* This routine enables the interrupt used by the CS8900 at the system level.  
* For the i386/i486 BSPs, this is done by making the system call 
* sysIntEnablePIC to enable the CS8900's interrupt at the 8259 PIC.
*
* RETURNS: OK or ERROR
*/

LOCAL STATUS sysEnetIntEnable( CS_END_DEVICE *pCS )
{
#if CPU_FAMILY == ARM
	/* For ARM user:
	   Please make sure how to enable your ARM interrupt for CS8900. */
   /* Enable interrupt at the Interrupt Controller */
    int_enable(pCS->IntLevel);  /* modefied by syx*/
#else
   /* For generic processor */
   /*  intEnable(pCS->IntLevel); */

   /* Enable interrupt at the 8259 PIC */
   if ( sysIntEnablePIC(pCS->IntLevel) == ERROR )
   {
      return ERROR;
   }
#endif

   return OK;
}


/******************************************************************************
*
* sysEnetIntDisable - disable CS8900 interrupts at the system level
*
* This routine disables the interrupt used by the CS8900 at the system level.  
* For the i386/i486 BSPs, this is done by making the system call 
* sysIntDisablePIC to disable the CS8900's interrupt at the 8259 PIC.
*
* NOTE: This routine is not currently required by the CS8900 driver.
*
* RETURNS: OK or ERROR
*/

LOCAL STATUS sysEnetIntDisable( CS_END_DEVICE *pCS )
{
   
#if CPU_FAMILY == ARM
	/* For ARM user:
	   Please make sure how to disable your ARM interrupt for CS8900.*/
   /* disable interrupt at the Interrupt Controller */
  int_disable(pCS->IntLevel);/* turn off the GPIO IRQ bit*/
#else
   /* For generic processor */
   /*  intDisable(pCS->IntLevel); */

   if ( sysIntDisablePIC(pCS->IntLevel) == ERROR )
   {
      return ERROR;
   }
#endif

   return OK;
}

void   INT_UNLOCK(int lockKey)
{
#if CPU_FAMILY ==  ARM
/* For ARM User:
   Please modify these two functions to fit your board.*/
   int_enable(pCS->IntLevel); /*turn on the GPIO IRQ bit*/
#else
     intUnlock(lockKey);
#endif
}


int    INT_LOCK(void)
{
#if CPU_FAMILY ==  ARM
/* For ARM User:
   Please modify these two functions to fit your board.*/
   int_disable(pCS->IntLevel); /* turn off the GPIO IRQ bit*/
    return 0; 
#else
   return intLock();
#endif
}


/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *
 * Support routines for the above board-specific routines                      *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */


/*******************************************************************************
*
* csGetUnspecifiedParms
*
*
*/

LOCAL STATUS csGetUnspecifiedParms( CS_END_DEVICE *pCS )
{
   USHORT SelfStatus;
   USHORT ISAConfig;
   USHORT MemBase;
   USHORT AdapterConfig;
   USHORT XmitCtl;

   /* If all of these parameters were specified */
   if ( pCS->ConfigFlags!=0 && pCS->pPacketPage!=NULL && pCS->IntLevel!=0 &&
         pCS->MediaType!=0 )
      return OK;  /* Don't need to get anything from the EEPROM */

   /* Verify that the EEPROM is present and OK */
   SelfStatus = csReadPacketPage( pCS, PKTPG_SELF_ST );
   if ( !((SelfStatus & SELF_ST_EEP_PRES) && (SelfStatus & SELF_ST_EEP_OK)) )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - EEPROM is missing or bad\n",0,0,0,0,0,0);
#endif
      return ERROR;
   }

   /* Get ISA configuration from the EEPROM */
   if ( csReadEEPROM(pCS,EEPROM_ISA_CFG,&ISAConfig) == ERROR )
      return ERROR;

   /* Get adapter configuration from the EEPROM */
   if ( csReadEEPROM(pCS,EEPROM_ADPTR_CFG,&AdapterConfig) == ERROR )
      return ERROR;

   /* Get transmission control from the EEPROM */
   if ( csReadEEPROM(pCS,EEPROM_XMIT_CTL,&XmitCtl) == ERROR )
      return ERROR;

   /* If the configuration flags were not specified */
   if ( pCS->ConfigFlags == 0 )
   {
      /* Copy the memory mode flag */
      if ( ISAConfig & ISA_CFG_MEM_MODE )
         pCS->ConfigFlags |= CFGFLG_MEM_MODE;

      /* Copy the USE_SA flag */
      if ( ISAConfig & ISA_CFG_USE_SA )
         pCS->ConfigFlags |= CFGFLG_USE_SA;

      /* Copy the IO Channel Ready flag */
      if ( ISAConfig & ISA_CFG_IOCHRDY )
         pCS->ConfigFlags |= CFGFLG_IOCHRDY;

      /* Copy the DC/DC Polarity flag */
      if ( AdapterConfig & ADPTR_CFG_DCDC_POL )
         pCS->ConfigFlags |= CFGFLG_DCDC_POL;

      /* Copy the Full Duplex flag */
      if ( XmitCtl & XMIT_CTL_FDX )
         pCS->ConfigFlags |= CFGFLG_FDX;
   }

   /* If the PacketPage pointer was not specified */
   if ( pCS->pPacketPage == NULL )
   {
      /* If memory mode is enabled */
      if ( pCS->ConfigFlags & CFGFLG_MEM_MODE )
      {
         /* Get the memory base address from EEPROM */
         if ( csReadEEPROM(pCS,EEPROM_MEM_BASE,&MemBase) == ERROR )
            return ERROR;

         MemBase &= MEM_BASE_MASK;  /* Clear unused bits */

         /* Setup the PacketPage pointer */
         pCS->pPacketPage = (unsigned short *)(((ULONG)MemBase)<<8);
      }
   }

#if CPU_FAMILY == I80X86
   /* If the interrupt level was not specified */
   if ( pCS->IntLevel == 0 )
   {
      /* Get the interrupt level from the ISA config */
      pCS->IntLevel = ISAConfig & ISA_CFG_IRQ_MASK;
      if ( pCS->IntLevel == 3 )
         pCS->IntLevel = 5;
      else
         pCS->IntLevel += 10;
   }
#endif

   /* If the media type was not specified */
   if ( pCS->MediaType == 0 )
   {
      switch( AdapterConfig & ADPTR_CFG_MEDIA )
      {
         case ADPTR_CFG_AUI:
            pCS->MediaType = MEDIA_AUI;
            break;
         case ADPTR_CFG_10BASE2:
            pCS->MediaType = MEDIA_10BASE2;
            break;
         case ADPTR_CFG_10BASET:
         default:
            pCS->MediaType = MEDIA_10BASET;
            break;
      }
   }

   return OK;
}


/*******************************************************************************
*
* csValidateParms
*
* This routine verifies that the memory address, interrupt level and media
* type are valid.  If any of these parameters are invalid, then and error
* message is printed and ERROR is returned.
*
*/

LOCAL STATUS csValidateParms( CS_END_DEVICE *pCS )
{
   int MemAddr;

   MemAddr = (int)(pCS->pPacketPage);

   if ( (MemAddr & 0x000FFF) != 0 )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - Memory address (0x%X) must start on a 4K boundry\n",
            MemAddr,0,0,0,0,0);
#endif
      return ERROR;
   }

#if CPU_FAMILY == I80X86
   if ( MemAddr > 0xFFF000 )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - Memory address (0x%X) is too large\n", MemAddr,0,0,0,0,0 );
#endif
      return ERROR;
   }

   if ( !(pCS->IntLevel==5 || pCS->IntLevel==10 || pCS->IntLevel==11 ||
         pCS->IntLevel==12) )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - Interrupt level (%d) is invalid\n", pCS->IntLevel,0,0,0,0,0 );
#endif
      return ERROR;
   }
#endif

   if ( !(pCS->MediaType==MEDIA_AUI || pCS->MediaType==MEDIA_10BASE2 ||
         pCS->MediaType==MEDIA_10BASET) )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - Media type (%d) is invalid\n", pCS->MediaType,0,0,0,0,0);
#endif
      return ERROR;
   }

   return OK;
}




/*******************************************************************************
*
* csReadEEPROM
*
* This routine reads a word from the EEPROM at the specified offset.
*
*/

LOCAL STATUS csReadEEPROM( CS_END_DEVICE *pCS, USHORT Offset, USHORT *pValue )
{
   int x;

   /* Ensure that the EEPROM is not busy */
   for ( x=0; x < MAXLOOP; x++ )
      if ( !(csReadPacketPage(pCS,PKTPG_SELF_ST)&SELF_ST_SI_BUSY) )
         break;
   if ( x == MAXLOOP )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - Can not read from EEPROM\n",0,0,0,0,0,0);
#endif
      return ERROR;
   }

   /* Issue the command to read the offset within the EEPROM */
   csWritePacketPage( pCS, PKTPG_EEPROM_CMD, Offset | EEPROM_CMD_READ );

   /* Wait until the command is completed */
   for ( x=0; x<MAXLOOP; x++ )
      if ( !(csReadPacketPage(pCS,PKTPG_SELF_ST)&SELF_ST_SI_BUSY) )
         break;
   if ( x == MAXLOOP )
   {
#ifdef CS_DEBUG_ENABLE
      logMsg("\ncs0 - Can not read from EEPROM\n",0,0,0,0,0,0);
#endif
      return ERROR;
   }

   /* Get the EEPROM data from the EEPROM Data register */
   *pValue = csReadPacketPage( pCS, PKTPG_EEPROM_DATA );

   return OK;
}


/*add by syx*/   /*to be add to sysLib.c*/
void CS_end_Init(void)
{
unsigned int *vEXTINT1  = (unsigned int *)EXTINT1;
unsigned int *vGPGCON  = (unsigned int *)GPGCON;
unsigned int *vBWSCON = (unsigned int *)BWSCON;
unsigned int *vBANKCON2= (unsigned int *)BANKCON2;
*vGPGCON=(*vGPGCON)&((~3)<<2)|(2<<2);*vEXTINT1=(*vEXTINT1)&((~0xf)<<4)|(4<<4);

*vBWSCON=(*vBWSCON)&((~0x3)<<8)|(1<<8); 
*vBWSCON=(*vBWSCON)&((~0x3)<<14)|(1<<14); /* 設置網卡芯片所在BANK2的位寬為16bit,使用NWAIT信號,不使用 UB/LB */
*vBANKCON2=0x00000C00;

}
/*end add*/