//  extended_mode = 1'b1;//  write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)  write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode  /* Set Acceptance Code and Acceptance Mask registers  write_register(8'd16, 8'ha6); // acceptance code 0  write_register(8'd17, 8'hb0); // acceptance code 1  write_register(8'd18, 8'h12); // acceptance code 2  write_register(8'd19, 8'h30); // acceptance code 3  write_register(8'd20, 8'hff); // acceptance mask 0  write_register(8'd21, 8'hff); // acceptance mask 1  write_register(8'd22, 8'hff); // acceptance mask 2  write_register(8'd23, 8'hff); // acceptance mask 3  write_register2(8'd16, 8'ha6); // acceptance code 0  write_register2(8'd17, 8'hb0); // acceptance code 1  write_register2(8'd18, 8'h12); // acceptance code 2  write_register2(8'd19, 8'h30); // acceptance code 3  write_register2(8'd20, 8'hff); // acceptance mask 0  write_register2(8'd21, 8'hff); // acceptance mask 1  write_register2(8'd22, 8'hff); // acceptance mask 2  write_register2(8'd23, 8'hff); // acceptance mask 3*/  // Set Acceptance Code and Acceptance Mask registers  write_register(8'd4, 8'he8); // acceptance code  write_register(8'd5, 8'h0f); // acceptance mask    #10;  repeat (1000) @ (posedge clk);    // Switch-off reset mode  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});  write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible                                  // This difference is resynchronized later.  // After exiting the reset mode sending bus free  repeat (11) send_bit(1);//  test_synchronization;       // test currently switched off//  test_empty_fifo_ext;        // test currently switched off//  test_full_fifo_ext;         // test currently switched off//  send_frame_ext;             // test currently switched off//  test_empty_fifo;            // test currently switched off//  test_full_fifo;             // test currently switched off//  test_reset_mode;              // test currently switched off//  bus_off_test;               // test currently switched off//  forced_bus_off;             // test currently switched off//  send_frame_basic;           // test currently switched on//  send_frame_extended;        // test currently switched off//  self_reception_request;       // test currently switched off//  manual_frame_basic;         // test currently switched off//  manual_frame_ext;           // test currently switched off//    error_test;//    register_test;    bus_off_recovery_test;/*  #5000;  $display("\n\nStart rx/tx err cnt\n");  -> igor;   // Switch-off reset mode  $display("Rest mode ON");  write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});  $display("Set extended mode");  extended_mode = 1'b1;  write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the extended mode  $display("Rest mode OFF");  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});  write_register(8'd14, 8'hde); // rx err cnt  write_register(8'd15, 8'had); // tx err cnt  read_register(8'd14, tmp_data); // rx err cnt  read_register(8'd15, tmp_data); // tx err cnt  // Switch-on reset mode  $display("Switch-on reset mode");  write_register(8'd0, {7'h0, `CAN_MODE_RESET});  write_register(8'd14, 8'h12); // rx err cnt  write_register(8'd15, 8'h34); // tx err cnt  read_register(8'd14, tmp_data); // rx err cnt  read_register(8'd15, tmp_data); // tx err cnt  // Switch-off reset mode  $display("Switch-off reset mode");  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});  read_register(8'd14, tmp_data); // rx err cnt  read_register(8'd15, tmp_data); // tx err cnt  // Switch-on reset mode  $display("Switch-on reset mode");  write_register(8'd0, {7'h0, `CAN_MODE_RESET});  write_register(8'd14, 8'h56); // rx err cnt  write_register(8'd15, 8'h78); // tx err cnt  // Switch-off reset mode  $display("Switch-off reset mode");  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});  read_register(8'd14, tmp_data); // rx err cnt  read_register(8'd15, tmp_data); // tx err cnt*/  #1000;  $display("CAN Testbench finished !");  $stop;endtask bus_off_recovery_test;  begin    -> igor;    // Switch-on reset mode    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});    // Set Clock Divider register    extended_mode = 1'b1;    write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)    write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)    write_register(8'd16, 8'h00); // acceptance code 0    write_register(8'd17, 8'h00); // acceptance code 1    write_register(8'd18, 8'h00); // acceptance code 2    write_register(8'd19, 8'h00); // acceptance code 3    write_register(8'd20, 8'hff); // acceptance mask 0    write_register(8'd21, 8'hff); // acceptance mask 1    write_register(8'd22, 8'hff); // acceptance mask 2    write_register(8'd23, 8'hff); // acceptance mask 3    write_register2(8'd16, 8'h00); // acceptance code 0    write_register2(8'd17, 8'h00); // acceptance code 1    write_register2(8'd18, 8'h00); // acceptance code 2    write_register2(8'd19, 8'h00); // acceptance code 3    write_register2(8'd20, 8'hff); // acceptance mask 0    write_register2(8'd21, 8'hff); // acceptance mask 1    write_register2(8'd22, 8'hff); // acceptance mask 2    write_register2(8'd23, 8'hff); // acceptance mask 3    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    // Enable all interrupts    write_register(8'd4, 8'hff); // irq enable register    repeat (30) send_bit(1);    -> igor;    $display("(%0t) CAN should be idle now", $time);    // Node 2 sends a message    write_register2(8'd16, 8'h83); // tx registers    write_register2(8'd17, 8'h12); // tx registers    write_register2(8'd18, 8'h34); // tx registers    write_register2(8'd19, 8'h45); // tx registers    write_register2(8'd20, 8'h56); // tx registers    write_register2(8'd21, 8'hde); // tx registers    write_register2(8'd22, 8'had); // tx registers    write_register2(8'd23, 8'hbe); // tx registers    write_register2(8'd1, 8'h1);  // tx request    // Wait until node 1 receives rx irq    read_register(8'd3, tmp_data);    while (!(tmp_data & 8'h01)) begin      read_register(8'd3, tmp_data);    end    $display("Frame received by node 1.");    // Node 1 will send a message and will receive many errors    write_register(8'd16, 8'haa); // tx registers    write_register(8'd17, 8'haa); // tx registers    write_register(8'd18, 8'haa); // tx registers    write_register(8'd19, 8'haa); // tx registers    write_register(8'd20, 8'haa); // tx registers    write_register(8'd21, 8'haa); // tx registers    write_register(8'd22, 8'haa); // tx registers    write_register(8'd23, 8'haa); // tx registers    fork       begin        write_register(8'd1, 8'h1);  // tx request      end      begin        // Waiting until node 1 starts transmitting        wait (!tx_i);        repeat (33) send_bit(1);        repeat (330) send_bit(0);        repeat (1) send_bit(1);      end    join    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    repeat (1999) send_bit(1);    // Switch-on reset mode    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});    write_register(8'd14, 8'h0); // rx err cnt    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    // Wait some time before simulation ends    repeat (10000) @ (posedge clk);  endendtask // bus_off_recovery_testtask error_test;  begin    // Switch-off reset mode    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});    // Set Clock Divider register    extended_mode = 1'b1;    write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)    write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)    // Set error warning limit register    write_register(8'd13, 8'h56); // error warning limit    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    // Enable all interrupts    write_register(8'd4, 8'hff); // irq enable register    repeat (300) send_bit(0);    $display("Kr neki");  endendtasktask register_test;  integer i, j, tmp;  begin    $display("Change mode to extended mode and test registers");    // Switch-off reset mode    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});    // Set Clock Divider register    extended_mode = 1'b1;    write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)    write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    for (i=1; i<128; i=i+1) begin      for (j=0; j<8; j=j+1) begin        read_register(i, tmp_data);        write_register(i, tmp_data | (1 << j));      end    end  endendtasktask forced_bus_off;    // Forcing bus-off by writinf to tx_err_cnt register  begin    // Switch-on reset mode    write_register(8'd0, {7'h0, `CAN_MODE_RESET});    // Set Clock Divider register    write_register(8'd31, {1'b1, 7'h0});    // Setting the extended mode (not normal)    // Write 255 to tx_err_cnt register - Forcing bus-off    write_register(8'd15, 255);    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});//    #1000000;    #2500000;    // Switch-on reset mode    write_register(8'd0, {7'h0, `CAN_MODE_RESET});    // Write 245 to tx_err_cnt register    write_register(8'd15, 245);    // Switch-off reset mode    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    #1000000;  endendtask   // forced_bus_offtask manual_frame_basic;    // Testbench sends a basic format frame  begin    // Switch-on reset mode    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});      // Set Acceptance Code and Acceptance Mask registers    write_register(8'd4, 8'h28); // acceptance code    write_register(8'd5, 8'hff); // acceptance mask        repeat (100) @ (posedge clk);        // Switch-off reset mode//    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});    write_register(8'd0, 8'h1e);  // reset_off, all irqs enabled.    // After exiting the reset mode sending bus free    repeat (11) send_bit(1);    write_register(8'd10, 8'h55); // Writing ID[10:3] = 0x55    write_register(8'd11, 8'h77); // Writing ID[2:0] = 0x3, rtr = 1, length = 7    write_register(8'd12, 8'h00); // data byte 1    write_register(8'd13, 8'h00); // data byte 2    write_register(8'd14, 8'h00); // data byte 3    write_register(8'd15, 8'h00); // data byte 4    write_register(8'd16, 8'h00); // data byte 5    write_register(8'd17, 8'h00); // data byte 6    write_register(8'd18, 8'h00); // data byte 7    write_register(8'd19, 8'h00); // data byte 8    tx_bypassed = 0;    // When this signal is on, tx is not looped back to the rx.        fork      begin        tx_request_command;//        self_reception_request_command;      end      begin        #931;        repeat (1)        begin          send_bit(0);  // SOF          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID arbi lost          send_bit(1);  // RTR          send_bit(0);  // IDE          send_bit(0);  // r0          send_bit(0);  // DLC          send_bit(1);  // DLC          send_bit(1);  // DLC          send_bit(1);  // DLC          send_bit(1);  // CRC          send_bit(1);  // CRC          send_bit(0);  // CRC stuff          send_bit(0);  // CRC 6          send_bit(0);  // CRC          send_bit(0);  // CRC          send_bit(0);  // CRC          send_bit(1);  // CRC  stuff          send_bit(0);  // CRC 0          send_bit(0);  // CRC          send_bit(1);  // CRC          send_bit(0);  // CRC          send_bit(1);  // CRC 5          send_bit(1);  // CRC          send_bit(0);  // CRC          send_bit(1);  // CRC          send_bit(1);  // CRC b          send_bit(1);  // CRC DELIM          send_bit(0);  // ACK          send_bit(1);  // ACK DELIM          send_bit(1);  // EOF          send_bit(1);  // EOF          send_bit(1);  // EOF          send_bit(1);  // EOF          send_bit(1);  // EOF          send_bit(1);  // EOF          send_bit(1);  // EOF          send_bit(1);  // INTER          send_bit(1);  // INTER          send_bit(1);  // INTER#400;          send_bit(0);  // SOF          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(0);  // ID          send_bit(1);  // ID          send_bit(1);  // ID          send_bit(1);  // RTR          send_bit(0);  // IDE          send_bit(0);  // r0          send_bit(0);  // DLC          send_bit(1);  // DLC          send_bit(1);  // DLC          send_bit(1);  // DLC