/* End: Tx data registers */reg           tx_successful_q;reg           overrun_q;reg           overrun_status;reg           transmission_complete;reg           transmit_buffer_status_q;reg           receive_buffer_status;reg           error_status_q;reg           node_bus_off_q;reg           node_error_passive_q;reg           transmit_buffer_status;reg           single_shot_transmission;reg           self_rx_request;reg           irq_n;// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.wire          data_overrun_irq_en;wire          error_warning_irq_en;wire          transmit_irq_en;wire          receive_irq_en;wire    [7:0] irq_reg;wire          irq;wire we_mode                  = cs & we & (addr == 8'd0);wire we_command               = cs & we & (addr == 8'd1);wire we_bus_timing_0          = cs & we & (addr == 8'd6) & reset_mode;wire we_bus_timing_1          = cs & we & (addr == 8'd7) & reset_mode;wire we_clock_divider_low     = cs & we & (addr == 8'd31);wire we_clock_divider_hi      = we_clock_divider_low & reset_mode;wire read = cs & (~we);wire read_irq_reg = read & (addr == 8'd3);assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 8'd11);assign read_error_code_capture_reg = read & extended_mode & (addr == 8'd12);/* This section is for BASIC and EXTENDED mode */wire we_acceptance_code_0       = cs & we &   reset_mode  & ((~extended_mode) & (addr == 8'd4)  | extended_mode & (addr == 8'd16));wire we_acceptance_mask_0       = cs & we &   reset_mode  & ((~extended_mode) & (addr == 8'd5)  | extended_mode & (addr == 8'd20));wire we_tx_data_0               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16)) & transmit_buffer_status;wire we_tx_data_1               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17)) & transmit_buffer_status;wire we_tx_data_2               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18)) & transmit_buffer_status;wire we_tx_data_3               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19)) & transmit_buffer_status;wire we_tx_data_4               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20)) & transmit_buffer_status;wire we_tx_data_5               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21)) & transmit_buffer_status;wire we_tx_data_6               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status;wire we_tx_data_7               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23)) & transmit_buffer_status;wire we_tx_data_8               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24)) & transmit_buffer_status;wire we_tx_data_9               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25)) & transmit_buffer_status;wire we_tx_data_10              = cs & we & (~reset_mode) & (                                     extended_mode & (addr == 8'd26)) & transmit_buffer_status;wire we_tx_data_11              = cs & we & (~reset_mode) & (                                     extended_mode & (addr == 8'd27)) & transmit_buffer_status;wire we_tx_data_12              = cs & we & (~reset_mode) & (                                     extended_mode & (addr == 8'd28)) & transmit_buffer_status;/* End: This section is for BASIC and EXTENDED mode *//* This section is for EXTENDED mode */wire   we_interrupt_enable      = cs & we & (addr == 8'd4)  & extended_mode;wire   we_error_warning_limit   = cs & we & (addr == 8'd13) & reset_mode & extended_mode;assign we_rx_err_cnt            = cs & we & (addr == 8'd14) & reset_mode & extended_mode;assign we_tx_err_cnt            = cs & we & (addr == 8'd15) & reset_mode & extended_mode;wire   we_acceptance_code_1     = cs & we & (addr == 8'd17) & reset_mode & extended_mode;wire   we_acceptance_code_2     = cs & we & (addr == 8'd18) & reset_mode & extended_mode;wire   we_acceptance_code_3     = cs & we & (addr == 8'd19) & reset_mode & extended_mode;wire   we_acceptance_mask_1     = cs & we & (addr == 8'd21) & reset_mode & extended_mode;wire   we_acceptance_mask_2     = cs & we & (addr == 8'd22) & reset_mode & extended_mode;wire   we_acceptance_mask_3     = cs & we & (addr == 8'd23) & reset_mode & extended_mode;/* End: This section is for EXTENDED mode */always @ (posedge clk)begin  tx_successful_q           <=#Tp tx_successful;  overrun_q                 <=#Tp overrun;  transmit_buffer_status_q  <=#Tp transmit_buffer_status;  error_status_q            <=#Tp error_status;  node_bus_off_q            <=#Tp node_bus_off;  node_error_passive_q      <=#Tp node_error_passive;end/* Mode register */wire   [0:0] mode;wire   [4:1] mode_basic;wire   [3:1] mode_ext;wire         receive_irq_en_basic;wire         transmit_irq_en_basic;wire         error_irq_en_basic;wire         overrun_irq_en_basic;can_register_asyn_syn #(1, 1'h1) MODE_REG0( .data_in(data_in[0]),  .data_out(mode[0]),  .we(we_mode),  .clk(clk),  .rst(rst),  .rst_sync(set_reset_mode));can_register_asyn #(4, 0) MODE_REG_BASIC( .data_in(data_in[4:1]),  .data_out(mode_basic[4:1]),  .we(we_mode),  .clk(clk),  .rst(rst));can_register_asyn #(3, 0) MODE_REG_EXT( .data_in(data_in[3:1]),  .data_out(mode_ext[3:1]),  .we(we_mode & reset_mode),  .clk(clk),  .rst(rst));assign reset_mode             = mode[0];assign listen_only_mode       = extended_mode & mode_ext[1];assign self_test_mode         = extended_mode & mode_ext[2];assign acceptance_filter_mode = extended_mode & mode_ext[3];assign receive_irq_en_basic  = mode_basic[1];assign transmit_irq_en_basic = mode_basic[2];assign error_irq_en_basic    = mode_basic[3];assign overrun_irq_en_basic  = mode_basic[4];/* End Mode register *//* Command register */wire   [4:0] command;can_register_asyn_syn #(1, 1'h0) COMMAND_REG0( .data_in(data_in[0]),  .data_out(command[0]),  .we(we_command),  .clk(clk),  .rst(rst),  .rst_sync(command[0] & sample_point | reset_mode));can_register_asyn_syn #(1, 1'h0) COMMAND_REG1( .data_in(data_in[1]),  .data_out(command[1]),  .we(we_command),  .clk(clk),  .rst(rst),  .rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)) | reset_mode));can_register_asyn_syn #(2, 2'h0) COMMAND_REG( .data_in(data_in[3:2]),  .data_out(command[3:2]),  .we(we_command),  .clk(clk),  .rst(rst),  .rst_sync(|command[3:2] | reset_mode));can_register_asyn_syn #(1, 1'h0) COMMAND_REG4( .data_in(data_in[4]),  .data_out(command[4]),  .we(we_command),  .clk(clk),  .rst(rst),  .rst_sync(command[4] & sample_point | reset_mode));always @ (posedge clk or posedge rst)begin  if (rst)    self_rx_request <= 1'b0;  else if (command[4] & (~command[0]))    self_rx_request <=#Tp 1'b1;  else if ((~tx_state) & tx_state_q)    self_rx_request <=#Tp 1'b0;endassign clear_data_overrun = command[3];assign release_buffer = command[2];assign tx_request = command[0] | command[4];assign abort_tx = command[1] & (~tx_request);always @ (posedge clk or posedge rst)begin  if (rst)    single_shot_transmission <= 1'b0;  else if (tx_request & command[1] & sample_point)    single_shot_transmission <=#Tp 1'b1;  else if ((~tx_state) & tx_state_q)    single_shot_transmission <=#Tp 1'b0;end/*can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD  // Uncomment this to enable overload requests !!!( .data_in(data_in[5]),  .data_out(overload_request),  .we(we_command),  .clk(clk),  .rst(rst),  .rst_sync(overload_frame & ~overload_frame_q));reg           overload_frame_q;always @ (posedge clk or posedge rst)begin  if (rst)    overload_frame_q <= 1'b0;  else    overload_frame_q <=#Tp overload_frame;end*/assign overload_request = 0;  // Overload requests are not supported, yet !!!/* End Command register *//* Status register */wire   [7:0] status;assign status[7] = node_bus_off;assign status[6] = error_status;assign status[5] = transmit_status;assign status[4] = receive_status;assign status[3] = transmission_complete;assign status[2] = transmit_buffer_status;assign status[1] = overrun_status;assign status[0] = receive_buffer_status;always @ (posedge clk or posedge rst)begin  if (rst)    transmission_complete <= 1'b1;  else if (tx_successful & (~tx_successful_q) | abort_tx)    transmission_complete <=#Tp 1'b1;  else if (tx_request)    transmission_complete <=#Tp 1'b0;endalways @ (posedge clk or posedge rst)begin  if (rst)    transmit_buffer_status <= 1'b1;  else if (tx_request)    transmit_buffer_status <=#Tp 1'b0;  else if (reset_mode || !need_to_tx)    transmit_buffer_status <=#Tp 1'b1;endalways @ (posedge clk or posedge rst)begin  if (rst)    overrun_status <= 1'b0;  else if (overrun & (~overrun_q))    overrun_status <=#Tp 1'b1;  else if (reset_mode || clear_data_overrun)    overrun_status <=#Tp 1'b0;endalways @ (posedge clk or posedge rst)begin  if (rst)    receive_buffer_status <= 1'b0;  else if (reset_mode || release_buffer)    receive_buffer_status <=#Tp 1'b0;  else if (~info_empty)    receive_buffer_status <=#Tp 1'b1;end/* End Status register *//* Interrupt Enable register (extended mode) */wire   [7:0] irq_en_ext;wire         bus_error_irq_en;wire         arbitration_lost_irq_en;wire         error_passive_irq_en;wire         data_overrun_irq_en_ext;wire         error_warning_irq_en_ext;wire         transmit_irq_en_ext;wire         receive_irq_en_ext;can_register #(8) IRQ_EN_REG( .data_in(data_in),  .data_out(irq_en_ext),  .we(we_interrupt_enable),  .clk(clk));assign bus_error_irq_en             = irq_en_ext[7];assign arbitration_lost_irq_en      = irq_en_ext[6];assign error_passive_irq_en         = irq_en_ext[5];assign data_overrun_irq_en_ext      = irq_en_ext[3];assign error_warning_irq_en_ext     = irq_en_ext[2];assign transmit_irq_en_ext          = irq_en_ext[1];assign receive_irq_en_ext           = irq_en_ext[0];/* End Bus Timing 0 register *//* Bus Timing 0 register */wire   [7:0] bus_timing_0;can_register #(8) BUS_TIMING_0_REG( .data_in(data_in),  .data_out(bus_timing_0),  .we(we_bus_timing_0),  .clk(clk));assign baud_r_presc = bus_timing_0[5:0];assign sync_jump_width = bus_timing_0[7:6];/* End Bus Timing 0 register *//* Bus Timing 1 register */wire   [7:0] bus_timing_1;can_register #(8) BUS_TIMING_1_REG( .data_in(data_in),  .data_out(bus_timing_1),  .we(we_bus_timing_1),  .clk(clk));assign time_segment1 = bus_timing_1[3:0];assign time_segment2 = bus_timing_1[6:4];assign triple_sampling = bus_timing_1[7];/* End Bus Timing 1 register *//* Error Warning Limit register */can_register_asyn #(8, 96) ERROR_WARNING_REG( .data_in(data_in),  .data_out(error_warning_limit),  .we(we_error_warning_limit),  .clk(clk),  .rst(rst));/* End Error Warning Limit register *//* Clock Divider register */wire   [7:0] clock_divider;wire         clock_off;wire   [2:0] cd;reg    [2:0] clkout_div;reg    [2:0] clkout_cnt;reg          clkout_tmp;can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7( .data_in(data_in[7]),  .data_out(clock_divider[7]),  .we(we_clock_divider_hi),  .clk(clk),  .rst(rst));assign clock_divider[6:4] = 3'h0;can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_3( .data_in(data_in[3]),  .data_out(clock_divider[3]),  .we(we_clock_divider_hi),  .clk(clk),  .rst(rst));can_register_asyn #(3, 0) CLOCK_DIVIDER_REG_LOW( .data_in(data_in[2:0]),  .data_out(clock_divider[2:0]),  .we(we_clock_divider_low),  .clk(clk),  .rst(rst));assign extended_mode = clock_divider[7];assign clock_off     = clock_divider[3];assign cd[2:0]       = clock_divider[2:0];always @ (cd)begin  case (cd)                       /* synthesis full_case parallel_case */     3'b000 : clkout_div = 3'd0;    3'b001 : clkout_div = 3'd1;    3'b010 : clkout_div = 3'd2;    3'b011 : clkout_div = 3'd3;    3'b100 : clkout_div = 3'd4;    3'b101 : clkout_div = 3'd5;    3'b110 : clkout_div = 3'd6;    3'b111 : clkout_div = 3'd0;  endcaseendalways @ (posedge clk or posedge rst)begin  if (rst)    clkout_cnt <= 3'h0;  else if (clkout_cnt == clkout_div)    clkout_cnt <=#Tp 3'h0;  else    clkout_cnt <= clkout_cnt + 1'b1;