endalways @ (posedge clk or posedge rst)begin  if (rst)    clkout_tmp <= 1'b0;  else if (clkout_cnt == clkout_div)    clkout_tmp <=#Tp ~clkout_tmp;endassign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);/* End Clock Divider register *//* This section is for BASIC and EXTENDED mode *//* Acceptance code register */can_register #(8) ACCEPTANCE_CODE_REG0( .data_in(data_in),  .data_out(acceptance_code_0),  .we(we_acceptance_code_0),  .clk(clk));/* End: Acceptance code register *//* Acceptance mask register */can_register #(8) ACCEPTANCE_MASK_REG0( .data_in(data_in),  .data_out(acceptance_mask_0),  .we(we_acceptance_mask_0),  .clk(clk));/* End: Acceptance mask register *//* End: This section is for BASIC and EXTENDED mode *//* Tx data 0 register. */can_register #(8) TX_DATA_REG0( .data_in(data_in),  .data_out(tx_data_0),  .we(we_tx_data_0),  .clk(clk));/* End: Tx data 0 register. *//* Tx data 1 register. */can_register #(8) TX_DATA_REG1( .data_in(data_in),  .data_out(tx_data_1),  .we(we_tx_data_1),  .clk(clk));/* End: Tx data 1 register. *//* Tx data 2 register. */can_register #(8) TX_DATA_REG2( .data_in(data_in),  .data_out(tx_data_2),  .we(we_tx_data_2),  .clk(clk));/* End: Tx data 2 register. *//* Tx data 3 register. */can_register #(8) TX_DATA_REG3( .data_in(data_in),  .data_out(tx_data_3),  .we(we_tx_data_3),  .clk(clk));/* End: Tx data 3 register. *//* Tx data 4 register. */can_register #(8) TX_DATA_REG4( .data_in(data_in),  .data_out(tx_data_4),  .we(we_tx_data_4),  .clk(clk));/* End: Tx data 4 register. *//* Tx data 5 register. */can_register #(8) TX_DATA_REG5( .data_in(data_in),  .data_out(tx_data_5),  .we(we_tx_data_5),  .clk(clk));/* End: Tx data 5 register. *//* Tx data 6 register. */can_register #(8) TX_DATA_REG6( .data_in(data_in),  .data_out(tx_data_6),  .we(we_tx_data_6),  .clk(clk));/* End: Tx data 6 register. *//* Tx data 7 register. */can_register #(8) TX_DATA_REG7( .data_in(data_in),  .data_out(tx_data_7),  .we(we_tx_data_7),  .clk(clk));/* End: Tx data 7 register. *//* Tx data 8 register. */can_register #(8) TX_DATA_REG8( .data_in(data_in),  .data_out(tx_data_8),  .we(we_tx_data_8),  .clk(clk));/* End: Tx data 8 register. *//* Tx data 9 register. */can_register #(8) TX_DATA_REG9( .data_in(data_in),  .data_out(tx_data_9),  .we(we_tx_data_9),  .clk(clk));/* End: Tx data 9 register. *//* Tx data 10 register. */can_register #(8) TX_DATA_REG10( .data_in(data_in),  .data_out(tx_data_10),  .we(we_tx_data_10),  .clk(clk));/* End: Tx data 10 register. *//* Tx data 11 register. */can_register #(8) TX_DATA_REG11( .data_in(data_in),  .data_out(tx_data_11),  .we(we_tx_data_11),  .clk(clk));/* End: Tx data 11 register. *//* Tx data 12 register. */can_register #(8) TX_DATA_REG12( .data_in(data_in),  .data_out(tx_data_12),  .we(we_tx_data_12),  .clk(clk));/* End: Tx data 12 register. *//* This section is for EXTENDED mode *//* Acceptance code register 1 */can_register #(8) ACCEPTANCE_CODE_REG1( .data_in(data_in),  .data_out(acceptance_code_1),  .we(we_acceptance_code_1),  .clk(clk));/* End: Acceptance code register *//* Acceptance code register 2 */can_register #(8) ACCEPTANCE_CODE_REG2( .data_in(data_in),  .data_out(acceptance_code_2),  .we(we_acceptance_code_2),  .clk(clk));/* End: Acceptance code register *//* Acceptance code register 3 */can_register #(8) ACCEPTANCE_CODE_REG3( .data_in(data_in),  .data_out(acceptance_code_3),  .we(we_acceptance_code_3),  .clk(clk));/* End: Acceptance code register *//* Acceptance mask register 1 */can_register #(8) ACCEPTANCE_MASK_REG1( .data_in(data_in),  .data_out(acceptance_mask_1),  .we(we_acceptance_mask_1),  .clk(clk));/* End: Acceptance code register *//* Acceptance mask register 2 */can_register #(8) ACCEPTANCE_MASK_REG2( .data_in(data_in),  .data_out(acceptance_mask_2),  .we(we_acceptance_mask_2),  .clk(clk));/* End: Acceptance code register *//* Acceptance mask register 3 */can_register #(8) ACCEPTANCE_MASK_REG3( .data_in(data_in),  .data_out(acceptance_mask_3),  .we(we_acceptance_mask_3),  .clk(clk));/* End: Acceptance code register *//* End: This section is for EXTENDED mode */// Reading data from registersalways @ ( addr or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or           acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or           acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or           reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or            tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or            error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or           arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code         )begin  case({extended_mode, addr[4:0]})  /* synthesis parallel_case */     {1'h1, 5'd00} :  data_out = {4'b0000, mode_ext[3:1], mode[0]};      // extended mode    {1'h1, 5'd01} :  data_out = 8'h0;                                   // extended mode    {1'h1, 5'd02} :  data_out = status;                                 // extended mode    {1'h1, 5'd03} :  data_out = irq_reg;                                // extended mode    {1'h1, 5'd04} :  data_out = irq_en_ext;                             // extended mode    {1'h1, 5'd06} :  data_out = bus_timing_0;                           // extended mode    {1'h1, 5'd07} :  data_out = bus_timing_1;                           // extended mode    {1'h1, 5'd11} :  data_out = {3'h0, arbitration_lost_capture[4:0]};  // extended mode    {1'h1, 5'd12} :  data_out = error_capture_code;                     // extended mode    {1'h1, 5'd13} :  data_out = error_warning_limit;                    // extended mode    {1'h1, 5'd14} :  data_out = rx_err_cnt;                             // extended mode    {1'h1, 5'd15} :  data_out = tx_err_cnt;                             // extended mode    {1'h1, 5'd16} :  data_out = acceptance_code_0;                      // extended mode    {1'h1, 5'd17} :  data_out = acceptance_code_1;                      // extended mode    {1'h1, 5'd18} :  data_out = acceptance_code_2;                      // extended mode    {1'h1, 5'd19} :  data_out = acceptance_code_3;                      // extended mode    {1'h1, 5'd20} :  data_out = acceptance_mask_0;                      // extended mode    {1'h1, 5'd21} :  data_out = acceptance_mask_1;                      // extended mode    {1'h1, 5'd22} :  data_out = acceptance_mask_2;                      // extended mode    {1'h1, 5'd23} :  data_out = acceptance_mask_3;                      // extended mode    {1'h1, 5'd24} :  data_out = 8'h0;                                   // extended mode    {1'h1, 5'd25} :  data_out = 8'h0;                                   // extended mode    {1'h1, 5'd26} :  data_out = 8'h0;                                   // extended mode    {1'h1, 5'd27} :  data_out = 8'h0;                                   // extended mode    {1'h1, 5'd28} :  data_out = 8'h0;                                   // extended mode    {1'h1, 5'd29} :  data_out = {1'b0, rx_message_counter};             // extended mode    {1'h1, 5'd31} :  data_out = clock_divider;                          // extended mode    {1'h0, 5'd00} :  data_out = {3'b001, mode_basic[4:1], mode[0]};     // basic mode    {1'h0, 5'd01} :  data_out = 8'hff;                                  // basic mode    {1'h0, 5'd02} :  data_out = status;                                 // basic mode    {1'h0, 5'd03} :  data_out = {4'he, irq_reg[3:0]};                   // basic mode    {1'h0, 5'd04} :  data_out = reset_mode? acceptance_code_0 : 8'hff;  // basic mode    {1'h0, 5'd05} :  data_out = reset_mode? acceptance_mask_0 : 8'hff;  // basic mode    {1'h0, 5'd06} :  data_out = reset_mode? bus_timing_0 : 8'hff;       // basic mode    {1'h0, 5'd07} :  data_out = reset_mode? bus_timing_1 : 8'hff;       // basic mode    {1'h0, 5'd10} :  data_out = reset_mode? 8'hff : tx_data_0;          // basic mode    {1'h0, 5'd11} :  data_out = reset_mode? 8'hff : tx_data_1;          // basic mode    {1'h0, 5'd12} :  data_out = reset_mode? 8'hff : tx_data_2;          // basic mode    {1'h0, 5'd13} :  data_out = reset_mode? 8'hff : tx_data_3;          // basic mode    {1'h0, 5'd14} :  data_out = reset_mode? 8'hff : tx_data_4;          // basic mode    {1'h0, 5'd15} :  data_out = reset_mode? 8'hff : tx_data_5;          // basic mode    {1'h0, 5'd16} :  data_out = reset_mode? 8'hff : tx_data_6;          // basic mode    {1'h0, 5'd17} :  data_out = reset_mode? 8'hff : tx_data_7;          // basic mode    {1'h0, 5'd18} :  data_out = reset_mode? 8'hff : tx_data_8;          // basic mode    {1'h0, 5'd19} :  data_out = reset_mode? 8'hff : tx_data_9;          // basic mode    {1'h0, 5'd31} :  data_out = clock_divider;                          // basic mode    default :  data_out = 8'h0;                                   // the rest is read as 0  endcaseend// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.assign data_overrun_irq_en  = extended_mode ? data_overrun_irq_en_ext  : overrun_irq_en_basic;assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;assign transmit_irq_en      = extended_mode ? transmit_irq_en_ext      : transmit_irq_en_basic;assign receive_irq_en       = extended_mode ? receive_irq_en_ext       : receive_irq_en_basic;reg data_overrun_irq;always @ (posedge clk or posedge rst)begin  if (rst)    data_overrun_irq <= 1'b0;  else if (overrun & (~overrun_q) & data_overrun_irq_en)    data_overrun_irq <=#Tp 1'b1;  else if (reset_mode || read_irq_reg)    data_overrun_irq <=#Tp 1'b0;endreg transmit_irq;always @ (posedge clk or posedge rst)begin  if (rst)    transmit_irq <= 1'b0;  else if (reset_mode || read_irq_reg)    transmit_irq <=#Tp 1'b0;  else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)    transmit_irq <=#Tp 1'b1;endreg receive_irq;always @ (posedge clk or posedge rst)begin  if (rst)    receive_irq <= 1'b0;  else if ((~info_empty) & (~receive_irq) & receive_irq_en)    receive_irq <=#Tp 1'b1;  else if (reset_mode || release_buffer)    receive_irq <=#Tp 1'b0;endreg error_irq;always @ (posedge clk or posedge rst)begin  if (rst)    error_irq <= 1'b0;  else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)    error_irq <=#Tp 1'b1;  else if (read_irq_reg)    error_irq <=#Tp 1'b0;endreg bus_error_irq;always @ (posedge clk or posedge rst)begin  if (rst)    bus_error_irq <= 1'b0;  else if (set_bus_error_irq & bus_error_irq_en)    bus_error_irq <=#Tp 1'b1;  else if (reset_mode || read_irq_reg)    bus_error_irq <=#Tp 1'b0;endreg arbitration_lost_irq;always @ (posedge clk or posedge rst)begin  if (rst)    arbitration_lost_irq <= 1'b0;  else if (set_arbitration_lost_irq & arbitration_lost_irq_en)    arbitration_lost_irq <=#Tp 1'b1;  else if (reset_mode || read_irq_reg)    arbitration_lost_irq <=#Tp 1'b0;endreg error_passive_irq;always @ (posedge clk or posedge rst)begin  if (rst)    error_passive_irq <= 1'b0;  else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)    error_passive_irq <=#Tp 1'b1;  else if (reset_mode || read_irq_reg)    error_passive_irq <=#Tp 1'b0;endassign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, 1'b0, data_overrun_irq, error_irq, transmit_irq, receive_irq};assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq;always @ (posedge clk or posedge rst)begin  if (rst)    irq_n <= 1'b1;  else if (read_irq_reg || release_buffer)    irq_n <=#Tp 1'b1;  else if (irq)    irq_n <=#Tp 1'b0;endendmodule