library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity traffic isport(clk : in std_logic;       ql : out std_logic_vector(7 downto 0);       qh : out std_logic_vector(7 downto 0);     red : out std_logic := '0';     green : out std_logic := '1';     yellow : out std_logic );end traffic;architecture lights of traffic issignal timeh : std_logic_vector(3 downto 0) := "0101" ;signal timel : std_logic_vector(3 downto 0) := "1010" ;signal exc : bit := '1' ;begin   process (clk,timeh,timel,exc)   begin    if(timeh = "0000" and timel < "0011") then	      yellow <= '1' ;	      red <= '0' ;	      green <= '0' ; 	      ql <= "00000000" ;	      qh <= "00000000" ;	      	  else if(exc = '0') then	          red <= '1';	          yellow <= '0';	       else	          green <= '1' ;		  yellow <= '0' ;	       end if; 	       	       case timel is	       	       when "0000" => ql <= "00111111";	       when "0001" => ql <= "00000110";	       when "0010" => ql <= "01011011";	       when "0011" => ql <= "01001111";	       when "0100" => ql <= "01100110";	       when "0101" => ql <= "01101101";	       when "0110" => ql <= "01111101";	       when "0111" => ql <= "00000111";	       when "1000" => ql <= "01111111";	       when "1001" => ql <= "01101111";	       when others => ql <= "00000000";	       end case;          	       case timeh is	    	       when "0000" => qh <= "00111111";	       when "0001" => qh <= "00000110";	       when "0010" => qh <= "01011011";	       when "0011" => qh <= "01001111";	       when "0100" => qh <= "01100110";	       when "0101" => qh <= "01101101";	       when others => qh <= "00000000";	       end case;	  	  end if;       if(clk 'event and clk='1') then        if(timel = "0000") then	      timel <= "1001";	      if(timeh = "0000") then	         timeh <= "0101";	         exc <= NOT exc;	      else	         timeh <= timeh - '1' ;	      end if;	  else 	     timel <= timel - '1' ;	  end if;    	       end if;   end process;end lights;