?? intr.c
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// Copyright (c) David Vescovi. All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation. All rights reserved.
//------------------------------------------------------------------------------
//
// File: intr.h
//
// This file contains Gunstix board specific interrupt code.
//
//------------------------------------------------------------------------------
#include "bsp.h"
// Global Variables
static volatile INTC_REG_T *g_pINTCRegs = NULL;
static volatile GPIO_REG_T *g_pGPIORegs = NULL;
static volatile OST_REG_T *g_pOSTRegs = NULL;
//------------------------------------------------------------------------------
//
// Function: BSPIntrInit
//
//------------------------------------------------------------------------------
BOOL BSPIntrInit()
{
UINT32 *pHardware;
OALMSG(OAL_INTR&&OAL_FUNC, (L"+BSPIntrInit\r\n"));
g_pINTCRegs = (volatile INTC_REG_T *)OALPAtoVA(PXA255_BASE_REG_PA_INTC, FALSE);
g_pGPIORegs = (volatile GPIO_REG_T *)OALPAtoVA(PXA255_BASE_REG_PA_GPIO, FALSE);
g_pOSTRegs = (volatile OST_REG_T *) OALPAtoVA(PXA255_BASE_REG_PA_OST, FALSE);
// Set up static interrupt mappings
pHardware = (UINT32 *) OALArgsQuery(BSP_ARGS_QUERY_HARDWARE);
OALMSG(OAL_INTR, (L"hardware 0x%08x\r\n",*pHardware));
OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIO84_2_UCB1400);
OALIntrStaticTranslate(SYSINTR_TOUCH_CHANGED, IRQ_OSMR1);
/*
if (*pHardware & GUMCFG_TOUCH)
{ // set touch interrupt
SETREG32(&g_pGPIORegs->GRER0, GPIO_16_AUINTR);
OUTREG32(&g_pGPIORegs->GEDR0, GPIO_16_AUINTR);
OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIO84_2_UCB1400);
OALIntrStaticTranslate(SYSINTR_TOUCH_CHANGED, IRQ_OSMR1);
}
*/
SETREG32((PULONG)&g_pINTCRegs->ICMR, INTC_GPIO84_2);
OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrInit\r\n"));
return TRUE;
}
//------------------------------------------------------------------------------
BOOL BSPIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
BOOL rc = FALSE;
OALMSG(OAL_INTR&&OAL_FUNC, (
L"+BSPIntrRequestIrq(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n",
pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
pDevLoc->Pin, pCount, pIrqs
));
// Check for input params
if (pIrqs == NULL || pCount == NULL || *pCount < 1) goto Done;
switch (pDevLoc->IfcType) {
case Internal:
switch ((ULONG)pDevLoc->LogicalLoc)
{
case (SMSC_ETH1_PA_BASE_REG + 0x300):
pIrqs[0] = IRQ_GPIO84_2_ETH1;
*pCount = 1;
rc = TRUE;
break;
case (SMSC_ETH2_PA_BASE_REG + 0x300):
pIrqs[0] = IRQ_GPIO84_2_ETH2;
*pCount = 1;
rc = TRUE;
break;
// comment the next few lines if you want card based kitl to run in polled mode
case (PXA255_BASE_REG_PA_PCMCIA_S0_IO + 0x300):
pIrqs[0] = IRQ_GPIO84_2_PCCARD_S0;
*pCount = 1;
rc = TRUE;
break;
case (PXA255_BASE_REG_PA_PCMCIA_S1_IO + 0x300):
pIrqs[0] = IRQ_GPIO84_2_PCCARD_S1;
*pCount = 1;
rc = TRUE;
break;
}
break;
}
Done:
OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrRequestIrq(rc = %d)\r\n", rc));
return rc;
}
//------------------------------------------------------------------------------
//
// Function: BSPIntrEnableIrq
//
// This function is called from OALIntrEnableIrq to enable interrupt on
// secondary interrupt controller.
//
UINT32 BSPIntrEnableIrq(UINT32 irq)
{
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrEnableIrq(%d)\r\n", irq));
// Valid board-level interrupt?
if ((irq >= IRQ_PXA255_GPIO84_2_MIN) && (irq <= IRQ_PXA255_GPIO84_2_MAX))
{
switch (irq) {
case IRQ_GPIO84_2_ETH1:
SETREG32(&g_pGPIORegs->GRER1, GPIO_36_E1INTR);
break;
case IRQ_GPIO84_2_ETH2:
SETREG32(&g_pGPIORegs->GRER0, GPIO_27_E2INTR);
break;
case IRQ_GPIO84_2_UCB1400:
SETREG32(&g_pGPIORegs->GRER0, GPIO_16_AUINTR);
break;
//case IRQ_GPIO84_2_CDMMC:
// SETREG32(&g_pGPIORegs->GRER0, GPIO_22_nCDMMC);
// SETREG32(&g_pGPIORegs->GFER0, GPIO_22_nCDMMC);
// SETREG32(&g_pGPIORegs->GRER1, GPIO_54_nCDMMC);
// SETREG32(&g_pGPIORegs->GFER1, GPIO_54_nCDMMC);
// break;
case IRQ_GPIO84_2_PCCARD_S0:
SETREG32(&g_pGPIORegs->GFER0, GPIO_26_S0_READY_nIREQ);
break;
case IRQ_GPIO84_2_PCCARD_S1:
SETREG32(&g_pGPIORegs->GFER0, GPIO_27_S1_READY_nIREQ);
break;
}
// enabling the interrupt at the secondary controller is enough
// - no need to enable the PXA255 GPI84_2 interrupt.
irq = OAL_INTR_IRQ_UNDEFINED;
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrEnableIrq(irq = %d)\r\n", irq));
return irq;
}
//------------------------------------------------------------------------------
//
// Function: BSPIntrDisableIrq
//
// This function is called from OALIntrDisableIrq to disable interrupt on
// secondary interrupt controller.
//
UINT32 BSPIntrDisableIrq(UINT32 irq)
{
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDisableIrq(%d)\r\n", irq));
// Valid board-level interrupt?
if ((irq >= IRQ_PXA255_GPIO84_2_MIN) && (irq <= IRQ_PXA255_GPIO84_2_MAX))
{
switch (irq) {
case IRQ_GPIO84_2_ETH1:
CLRREG32(&g_pGPIORegs->GRER1, GPIO_36_E1INTR);
break;
case IRQ_GPIO84_2_ETH2:
CLRREG32(&g_pGPIORegs->GRER0, GPIO_27_E2INTR);
break;
case IRQ_GPIO84_2_UCB1400:
CLRREG32(&g_pGPIORegs->GRER0, GPIO_16_AUINTR);
break;
//case IRQ_GPIO84_2_CDMMC:
// CLRREG32(&g_pGPIORegs->GRER0, GPIO_22_nCDMMC);
// CLRREG32(&g_pGPIORegs->GFER0, GPIO_22_nCDMMC);
// CLRREG32(&g_pGPIORegs->GRER1, GPIO_54_nCDMMC);
// CLRREG32(&g_pGPIORegs->GFER1, GPIO_54_nCDMMC);
// break;
case IRQ_GPIO84_2_PCCARD_S0:
CLRREG32(&g_pGPIORegs->GFER0, GPIO_26_S0_READY_nIREQ);
break;
case IRQ_GPIO84_2_PCCARD_S1:
CLRREG32(&g_pGPIORegs->GFER0, GPIO_27_S1_READY_nIREQ);
break;
}
// Masking the interrupt at the secondary controller is enough
// - no need to disable the PXA255 GPI84_2 interrupt.
irq = OAL_INTR_IRQ_UNDEFINED;
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDisableIrq(irq = %d\r\n", irq));
return irq;
}
//------------------------------------------------------------------------------
//
// Function: BSPIntrDoneIrq
//
// This function is called from OALIntrDoneIrq to finish interrupt on
// secondary interrupt controller.
//
UINT32 BSPIntrDoneIrq(UINT32 irq)
{
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDoneIrq(%d)\r\n", irq));
// Valid board-level interrupt?
if (((irq >= IRQ_PXA255_GPIO84_2_MIN) && (irq <= IRQ_PXA255_GPIO84_2_MAX)) || irq == IRQ_OSMR1)
{
switch (irq) {
case IRQ_GPIO84_2_ETH1:
break;
case IRQ_GPIO84_2_ETH2:
break;
case IRQ_GPIO84_2_UCB1400:
break;
//case IRQ_GPIO84_2_CDMMC:
// SETREG32(&g_pGPIORegs->GRER0, GPIO_22_nCDMMC);
// SETREG32(&g_pGPIORegs->GFER0, GPIO_22_nCDMMC);
// SETREG32(&g_pGPIORegs->GRER1, GPIO_54_nCDMMC);
// SETREG32(&g_pGPIORegs->GFER1, GPIO_54_nCDMMC);
// break;
case IRQ_GPIO84_2_PCCARD_S0:
// SETREG32(&g_pGPIORegs->GFER0, GPIO_26_S0_READY_nIREQ);
break;
case IRQ_GPIO84_2_PCCARD_S1:
// SETREG32(&g_pGPIORegs->GFER0, GPIO_27_S1_READY_nIREQ);
break;
}
// enabling the interrupt at the secondary controller is enough
// - no need to enable the PXA255 GPI84_2 interrupt.
irq = OAL_INTR_IRQ_UNDEFINED;
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDoneIrq(irq = %d)\r\n", irq));
return irq;
}
//------------------------------------------------------------------------------
//
// Function: BSPIntrActiveIrq
//
// This function is called from interrupt handler to give BSP chance to
// translate IRQ in case of secondary interrupt controller.
//
UINT32 BSPIntrActiveIrq(UINT32 irq)
{
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrActiveIrq(%d)\r\n", irq));
switch(irq)
{
case IRQ_GPIO0:
break;
case IRQ_GPIO1:
break;
case IRQ_GPIO84_2:
// we have to check all sources of 2-84 interruprs
if (GPIO_36_E1INTR & INREG32(&g_pGPIORegs->GEDR1))
{ // reset interrupt
OUTREG32(&g_pGPIORegs->GEDR1, GPIO_36_E1INTR);
irq = IRQ_GPIO84_2_ETH1;
break;
}
else if (GPIO_27_E2INTR & INREG32(&g_pGPIORegs->GEDR0))
{ // reset interrupt
OUTREG32(&g_pGPIORegs->GEDR0, GPIO_27_E2INTR);
irq = IRQ_GPIO84_2_ETH2;
break;
}
else if (GPIO_16_AUINTR & INREG32(&g_pGPIORegs->GEDR0))
{ // reset interrupt
OUTREG32(&g_pGPIORegs->GEDR0, GPIO_16_AUINTR);
irq = IRQ_GPIO84_2_UCB1400;
break;
}
//else if ((GPIO_22_nCDMMC & INREG32(&g_pGPIORegs->GEDR0)) || (GPIO_54_nCDMMC & INREG32(&g_pGPIORegs->GEDR1)))
//{ // mask and clear interrupt
// CLRREG32(&g_pGPIORegs->GRER0, GPIO_22_nCDMMC);
// CLRREG32(&g_pGPIORegs->GFER0, GPIO_22_nCDMMC);
// OUTREG32(&g_pGPIORegs->GEDR0, GPIO_22_nCDMMC);
// CLRREG32(&g_pGPIORegs->GRER1, GPIO_54_nCDMMC);
// CLRREG32(&g_pGPIORegs->GFER1, GPIO_54_nCDMMC);
// OUTREG32(&g_pGPIORegs->GEDR1, GPIO_54_nCDMMC);
// irq = IRQ_GPIO84_2_CDMMC;
// break;
//}
else if (GPIO_26_S0_READY_nIREQ & INREG32(&g_pGPIORegs->GEDR0))
{ // reset interrupt
// SETREG32(&g_pGPIORegs->GFER0, GPIO_26_S0_READY_nIREQ);
OUTREG32(&g_pGPIORegs->GEDR0, GPIO_26_S0_READY_nIREQ);
irq = IRQ_GPIO84_2_PCCARD_S0;
break;
}
else if (GPIO_27_S1_READY_nIREQ & INREG32(&g_pGPIORegs->GEDR0))
{ // reset interrupt
// SETREG32(&g_pGPIORegs->GFER0, GPIO_27_S1_READY_nIREQ);
OUTREG32(&g_pGPIORegs->GEDR0, GPIO_27_S1_READY_nIREQ);
irq = IRQ_GPIO84_2_PCCARD_S0;
break;
}
break;
default:
break;
}
OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrActiveIrq(%d)\r\n", irq));
return irq;
}
//------------------------------------------------------------------------------
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