?? strata32.c
字號:
//====================================================================
// File Name : strata32.c
// Function : S3C2440 Intel Strata NOR Flash
// Program : Lee, Sang Jo (LSJ)
// Date : June 14, 2002
// Version : 0.0
// History
// 0.0 : Programming start (June 14, 2002) -> LSJ
// Arrangement source code(8/01/2002)-> SOP
//====================================================================
#include <stdlib.h>
#include <string.h>
#include "def.h"
#include "option.h"
#include "2410addr.h"
#include "2410lib.h"
#include "2410slib.h"
#include "strata32.h"
static void InputAddresses(void);
static int Strata_ProgFlash(U32 realAddr,U16 data);
static void Strata_EraseSector(int targetAddr);
static int Strata_CheckID(int targetAddr);
static int Strata_CheckDevice(int targetAddr);
static int Strata_CheckBlockLock(int targetAddr);
static int Strata_BlankCheck(int targetAddr,int targetSize);
//static int Strata_Display(int targetAddr,int targetSize);
extern U32 downloadAddress;
extern U32 downloadProgramSize;
static U32 srcAddress;
static U32 targetOffset;
static U32 targetAddress;
static U32 targetSize;
// Because S3C2440 is connected to Intel StrataFlash 28F128J3A,
// the addr parameter has to be a WORD address, so called in Intel specification.
// by chc
#define _WR(addr,data) *((volatile U16 *)(addr))=(U16)data
#define _RD(addr) ( *((volatile U16 *)(addr)) )
// _RESET() : Read Array
#define _RESET() _WR(targetAddress,0x00ff)
extern U32 downloadAddress;
extern U32 downloadProgramSize;
static int error_erase=0; // Read Status Register, SR.5
static int error_program=0; // Read Status Register, SR.4
//==========================================================================================
int Strata_CheckID(int targetAddr)
{
_RESET();
_WR(targetAddr, 0x0090);
return _RD(targetAddr); // Read Identifier Code, including lower, higher 16-bit, 8MB, Intel Strate Flash ROM
// targetAddress must be the beginning location of a Block Address
}
//==========================================================================================
int Strata_CheckDevice(int targetAddr)
{
_RESET();
_WR(targetAddr, 0x0090);
return _RD(targetAddr+0x2); // Read Device Code, including lower, higher 16-bit, 8MB, Intel Strate Flash ROM
// targetAddress must be the beginning location of a Block Address
}
//==========================================================================================
int Strata_CheckBlockLock(int targetAddr)
{
_RESET();
_WR(targetAddr, 0x0090);
return _RD(targetAddr+0x4); // Read Block Lock configuration,
// targetAddress must be the beginning location of a Block Address
}
void Strata_Unlock(int targetAddr)
{
_RESET();
_WR(targetAddr, 0x0060);
_WR(targetAddr, 0x00D0);
}
void Strata_SetBlockLock(int targetAddr)
{
_RESET();
_WR(targetAddr, 0x0060);
_WR(targetAddr, 0x0001);
}
//==========================================================================================
void Strata_EraseSector(int targetAddress)
{
unsigned long ReadStatus;
unsigned long bSR5; // Erase and Clear Lock-bits Status, lower 16bit, 8MB Intel Strate Flash ROM
unsigned long bSR7; // Write State Machine Status, lower 16bit, 8MB Intel Strate Flash ROM
_RESET();
_WR(targetAddress, 0x0020); // Block Erase, First Bus Cycle, targetAddress is the address withint the block
_WR(targetAddress, 0x00d0); // Block Erase, Second Bus Cycle, targetAddress is the address withint the block
_RESET();
_WR(targetAddress, 0x0070); // Read Status Register, First Bus Cycle, targetAddress is any valid address within the device
ReadStatus=_RD(targetAddress); // Read Status Register, Second Bus Cycle, targetAddress is any valid address within the device
bSR7=ReadStatus & (1<<7); // lower 16-bit 8MB Strata
while(!bSR7 )
{
_WR(targetAddress, 0x0070);
ReadStatus=_RD(targetAddress);
bSR7=ReadStatus & (1<<7);
// Uart_Printf("wait !!\n");
}
_WR(targetAddress, 0x0070); // When the block erase is complete, status register bit SR.5 should be checked.
// If a block erase error is detected, the status register should be cleared before
// system software attempts correct actions.
ReadStatus=_RD(targetAddress);
bSR5=ReadStatus & (1<<5); // lower 16-bit 8MB Strata
if (bSR5==0 )
{
Uart_Printf("Block_%x Erase O.K. \n",targetAddress);
}
else
{
Uart_Printf("Error in Block Erasure!!\n");
_WR(targetAddress, 0x0050); // Clear Status Register
error_erase=1; // But not major, is it casual ?
}
_RESET(); // write 0xffh(_RESET()) after the last opoeration to reset the device to read array mode.
}
//==========================================================================================
int Strata_BlankCheck(int targetAddr,int targetSize)
{
int i,j;
//
_RESET();
for (i=0; i<targetSize; i+=2)
{
j=(*((volatile U16 *)(i+targetAddr))) & 0xffff;
if (j!=0xffff) // In erasure it changes all block dta to 0xff
{
Uart_Printf("E : %x = %x\n", (i+targetAddr), j);
return 0;
}
}
return 1;
}
//==========================================================================================
int Strata_ProgFlash(U32 realAddr,U16 data)
{
volatile U16 *ptargetAddr;
unsigned long ReadStatus;
unsigned long bSR4; // Erase and Clear Lock-bits Status, lower 16bit, 8MB Intel Strate Flash ROM
unsigned long bSR7; // Write State Machine Status, lower 16bit, 8MB Intel Strate Flash ROM
ptargetAddr = (volatile U16 *)realAddr;
//
_RESET();
_WR(realAddr, 0x0040); // realAddr is any valid adress within the device
// Word/Byte Program(or 0x00100010 can be used)
*ptargetAddr=data; // 32 bit data
//
_RESET();
_WR(realAddr, 0x0070); // Read Status Register
ReadStatus=_RD(realAddr); // realAddr is any valid address within the device
bSR7=ReadStatus & (1<<7);
while(!bSR7 )
{
//
_RESET();
_WR(realAddr, 0x0070); // Read Status Register
ReadStatus=_RD(realAddr);
bSR7=ReadStatus & (1<<7);
}
_WR(realAddr, 0x0070);
ReadStatus=_RD(realAddr); // Real Status Register
bSR4=ReadStatus & (1<<4);
if (bSR4==0 )
{
//Uart_Printf("Successful Program!!\n");
}
else
{
Uart_Printf("Error Program!!\n");
_WR(realAddr, 0x0050); // Clear Status Register
error_program=1; // But not major, is it casual ?
}
_RESET();
return 0;
}
#define TARGET_ADDR_28F128 0x00000000 // nGCS4, 128MB area
#define SOURCE_ADDR_FOR_28F128 0x31000000 // After 16MB of SDRAM
// 0x30000000 - 0x30ffffff : Area for this test program
//==========================================================================================
void Program28F128J3A(void)
{
// FlashROM write program must reside at RAM region NOT ROM region
// In reading and writing all interrupts are disabled because the flash ROM
// strongly dislike to be disturbed by other stuff.
// And the region of flash ROM must be I/O region which means NO cacheable
// and NO bufferable in MMU. Check it out !!!
// 2001.6.18. Mon. It's local rain. I'll hope it eliminates the drought in Korea. by chc
int i, id1, id2;
Uart_Printf("\n[ Intel 28F320J3A Flash Writing Program ]\n\n");
rINTMSK = BIT_ALLMSK;
targetAddress=TARGET_ADDR_28F128;
targetSize=downloadProgramSize;
srcAddress=downloadAddress;
if(targetSize==0)
{
Uart_Printf("\nThe data must be downloaded using XMODEM from 0x31000000\n");
return;
}
InputAddresses(); //srcAddress,targetSize,targetOffset will be determined.
Uart_Printf("Source base address(0x31000000) = 0x%x\n",srcAddress);
Uart_Printf("Target base address(0x00000000) = 0x%x\n",targetAddress);
Uart_Printf("Target offset (0x0) = 0x%x\n",targetOffset);
Uart_Printf("Target size (0x20000*n) = 0x%x\n",targetSize);
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -