if (pPrt->PhyType != SK_PHY_XMAC) {		do {			XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);			/* wait until 'Ready' is set */		} while ((Mmu & XM_MMU_PHY_RDY) == 0);		/* get the PHY register's value */		XM_IN16(IoC, Port, XM_PHY_DATA, pVal);	}}	/* SkXmPhyRead *//****************************************************************************** * *	SkXmPhyWrite() - Write to XMAC PHY register * * Description:	writes a 16-bit word to XMAC PHY or ext. PHY * * Returns: *	nothing */void SkXmPhyWrite(SK_AC	*pAC,		/* Adapter Context */SK_IOC	IoC,		/* I/O Context */int		Port,		/* Port Index (MAC_1 + n) */int		PhyReg,		/* Register Address (Offset) */SK_U16	Val)		/* Value */{	SK_U16		Mmu;	SK_GEPORT	*pPrt;	pPrt = &pAC->GIni.GP[Port];	if (pPrt->PhyType != SK_PHY_XMAC) {		do {			XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);			/* wait until 'Busy' is cleared */		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);	}	/* write the PHY register's address */	XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);	/* write the PHY register's value */	XM_OUT16(IoC, Port, XM_PHY_DATA, Val);	if (pPrt->PhyType != SK_PHY_XMAC) {		do {			XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);			/* wait until 'Busy' is cleared */		} while ((Mmu & XM_MMU_PHY_BUSY) != 0);	}}	/* SkXmPhyWrite *//****************************************************************************** * *	SkGmPhyRead() - Read from GPHY register * * Description:	reads a 16-bit word from GPHY through MDIO * * Returns: *	nothing */void SkGmPhyRead(SK_AC	*pAC,		/* Adapter Context */SK_IOC	IoC,		/* I/O Context */int		Port,		/* Port Index (MAC_1 + n) */int		PhyReg,		/* Register Address (Offset) */SK_U16	*pVal)		/* Pointer to Value */{	SK_U16	Ctrl;	SK_GEPORT	*pPrt;#ifdef VCPU	u_long SimCyle;	u_long SimLowTime;	VCPUgetTime(&SimCyle, &SimLowTime);	VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",		PhyReg, SimCyle, SimLowTime);#endif /* VCPU */	pPrt = &pAC->GIni.GP[Port];	/* set PHY-Register offset and 'Read' OpCode (= 1) */	*pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |		GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);	GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);	GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);	/* additional check for MDC/MDIO activity */	if ((Ctrl & GM_SMI_CT_BUSY) == 0) {		*pVal = 0;		return;	}	*pVal |= GM_SMI_CT_BUSY;	do {#ifdef VCPU		VCPUwaitTime(1000);#endif /* VCPU */		GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);	/* wait until 'ReadValid' is set */	} while (Ctrl == *pVal);	/* get the PHY register's value */	GM_IN16(IoC, Port, GM_SMI_DATA, pVal);#ifdef VCPU	VCPUgetTime(&SimCyle, &SimLowTime);	VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",		SimCyle, SimLowTime);#endif /* VCPU */}	/* SkGmPhyRead *//****************************************************************************** * *	SkGmPhyWrite() - Write to GPHY register * * Description:	writes a 16-bit word to GPHY through MDIO * * Returns: *	nothing */void SkGmPhyWrite(SK_AC	*pAC,		/* Adapter Context */SK_IOC	IoC,		/* I/O Context */int		Port,		/* Port Index (MAC_1 + n) */int		PhyReg,		/* Register Address (Offset) */SK_U16	Val)		/* Value */{	SK_U16	Ctrl;	SK_GEPORT	*pPrt;#ifdef VCPU	SK_U32	DWord;	u_long	SimCyle;	u_long	SimLowTime;	VCPUgetTime(&SimCyle, &SimLowTime);	VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",		PhyReg, Val, SimCyle, SimLowTime);#endif /* VCPU */	pPrt = &pAC->GIni.GP[Port];	/* write the PHY register's value */	GM_OUT16(IoC, Port, GM_SMI_DATA, Val);	/* set PHY-Register offset and 'Write' OpCode (= 0) */	Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);	GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);	GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);	/* additional check for MDC/MDIO activity */	if ((Ctrl & GM_SMI_CT_BUSY) == 0) {		return;	}	Val |= GM_SMI_CT_BUSY;	do {#ifdef VCPU		/* read Timer value */		SK_IN32(IoC, B2_TI_VAL, &DWord);		VCPUwaitTime(1000);#endif /* VCPU */		GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);	/* wait until 'Busy' is cleared */	} while (Ctrl == Val);#ifdef VCPU	VCPUgetTime(&SimCyle, &SimLowTime);	VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",		SimCyle, SimLowTime);#endif /* VCPU */}	/* SkGmPhyWrite *//****************************************************************************** * *	SkGePhyRead() - Read from PHY register * * Description:	calls a read PHY routine dep. on board type * * Returns: *	nothing */void SkGePhyRead(SK_AC	*pAC,		/* Adapter Context */SK_IOC	IoC,		/* I/O Context */int		Port,		/* Port Index (MAC_1 + n) */int		PhyReg,		/* Register Address (Offset) */SK_U16	*pVal)		/* Pointer to Value */{	void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal);	if (pAC->GIni.GIGenesis) {		r_func = SkXmPhyRead;	}	else {		r_func = SkGmPhyRead;	}	r_func(pAC, IoC, Port, PhyReg, pVal);}	/* SkGePhyRead *//****************************************************************************** * *	SkGePhyWrite() - Write to PHY register * * Description:	calls a write PHY routine dep. on board type * * Returns: *	nothing */void SkGePhyWrite(SK_AC	*pAC,		/* Adapter Context */SK_IOC	IoC,		/* I/O Context */int		Port,		/* Port Index (MAC_1 + n) */int		PhyReg,		/* Register Address (Offset) */SK_U16	Val)		/* Value */{	void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val);	if (pAC->GIni.GIGenesis) {		w_func = SkXmPhyWrite;	}	else {		w_func = SkGmPhyWrite;	}	w_func(pAC, IoC, Port, PhyReg, Val);}	/* SkGePhyWrite *//****************************************************************************** * *	SkMacPromiscMode() - Enable / Disable Promiscuous Mode * * Description: *   enables / disables promiscuous mode by setting Mode Register (XMAC) or *   Receive Control Register (GMAC) dep. on board type * * Returns: *	nothing */void SkMacPromiscMode(SK_AC	*pAC,	/* adapter context */SK_IOC	IoC,	/* IO context */int		Port,	/* Port Index (MAC_1 + n) */SK_BOOL	Enable)	/* Enable / Disable */{	SK_U16	RcReg;	SK_U32	MdReg;	if (pAC->GIni.GIGenesis) {		XM_IN32(IoC, Port, XM_MODE, &MdReg);		/* enable or disable promiscuous mode */		if (Enable) {			MdReg |= XM_MD_ENA_PROM;		}		else {			MdReg &= ~XM_MD_ENA_PROM;		}		/* setup Mode Register */		XM_OUT32(IoC, Port, XM_MODE, MdReg);	}	else {		GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);		/* enable or disable unicast and multicast filtering */		if (Enable) {			RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);		}		else {			RcReg |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);		}		/* setup Receive Control Register */		GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg);	}}	/* SkMacPromiscMode*//****************************************************************************** * *	SkMacHashing() - Enable / Disable Hashing * * Description: *   enables / disables hashing by setting Mode Register (XMAC) or *   Receive Control Register (GMAC) dep. on board type * * Returns: *	nothing */void SkMacHashing(SK_AC	*pAC,	/* adapter context */SK_IOC	IoC,	/* IO context */int		Port,	/* Port Index (MAC_1 + n) */SK_BOOL	Enable)	/* Enable / Disable */{	SK_U16	RcReg;	SK_U32	MdReg;	if (pAC->GIni.GIGenesis) {		XM_IN32(IoC, Port, XM_MODE, &MdReg);		/* enable or disable hashing */		if (Enable) {			MdReg |= XM_MD_ENA_HASH;		}		else {			MdReg &= ~XM_MD_ENA_HASH;		}		/* setup Mode Register */		XM_OUT32(IoC, Port, XM_MODE, MdReg);	}	else {		GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);		/* enable or disable multicast filtering */		if (Enable) {			RcReg |= GM_RXCR_MCF_ENA;		}		else {			RcReg &= ~GM_RXCR_MCF_ENA;		}		/* setup Receive Control Register */		GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg);	}}	/* SkMacHashing*/#ifdef SK_DIAG/****************************************************************************** * *	SkXmSetRxCmd() - Modify the value of the XMAC's Rx Command Register * * Description: *	The features *	 - FCS stripping,					SK_STRIP_FCS_ON/OFF *	 - pad byte stripping,				SK_STRIP_PAD_ON/OFF *	 - don't set XMR_FS_ERR in status	SK_LENERR_OK_ON/OFF *	   for inrange length error frames *	 - don't set XMR_FS_ERR in status	SK_BIG_PK_OK_ON/OFF *	   for frames > 1514 bytes *   - enable Rx of own packets         SK_SELF_RX_ON/OFF * *	for incoming packets may be enabled/disabled by this function. *	Additional modes may be added later. *	Multiple modes can be enabled/disabled at the same time. *	The new configuration is written to the Rx Command register immediately. * * Returns: *	nothing */static void SkXmSetRxCmd(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Port,		/* Port Index (MAC_1 + n) */int		Mode)		/* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,					   SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */{	SK_U16	OldRxCmd;	SK_U16	RxCmd;	XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);	RxCmd = OldRxCmd;	switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {	case SK_STRIP_FCS_ON:		RxCmd |= XM_RX_STRIP_FCS;		break;	case SK_STRIP_FCS_OFF:		RxCmd &= ~XM_RX_STRIP_FCS;		break;	}	switch (Mode & (SK_STRIP_PAD_ON | SK_STRIP_PAD_OFF)) {	case SK_STRIP_PAD_ON:		RxCmd |= XM_RX_STRIP_PAD;		break;	case SK_STRIP_PAD_OFF:		RxCmd &= ~XM_RX_STRIP_PAD;		break;	}	switch (Mode & (SK_LENERR_OK_ON | SK_LENERR_OK_OFF)) {	case SK_LENERR_OK_ON:		RxCmd |= XM_RX_LENERR_OK;		break;	case SK_LENERR_OK_OFF:		RxCmd &= ~XM_RX_LENERR_OK;		break;	}	switch (Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) {	case SK_BIG_PK_OK_ON:		RxCmd |= XM_RX_BIG_PK_OK;		break;	case SK_BIG_PK_OK_OFF:		RxCmd &= ~XM_RX_BIG_PK_OK;		break;	}	switch (Mode & (SK_SELF_RX_ON | SK_SELF_RX_OFF)) {	case SK_SELF_RX_ON:		RxCmd |= XM_RX_SELF_RX;		break;	case SK_SELF_RX_OFF:		RxCmd &= ~XM_RX_SELF_RX;		break;	}	/* Write the new mode to the Rx command register if required */	if (OldRxCmd != RxCmd) {		XM_OUT16(IoC, Port, XM_RX_CMD, RxCmd);	}}	/* SkXmSetRxCmd *//****************************************************************************** * *	SkGmSetRxCmd() - Modify the value of the GMAC's Rx Control Register * * Description: *	The features *	 - FCS (CRC) stripping,				SK_STRIP_FCS_ON/OFF *	 - don't set GMR_FS_LONG_ERR		SK_BIG_PK_OK_ON/OFF *	   for frames > 1514 bytes *   - enable Rx of own packets         SK_SELF_RX_ON/OFF * *	for incoming packets may be enabled/disabled by this function. *	Additional modes may be added later. *	Multiple modes can be enabled/disabled at the same time. *	The new configuration is written to the Rx Command register immediately. * * Returns: *	nothing */static void SkGmSetRxCmd(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Port,		/* Port Index (MAC_1 + n) */int		Mode)		/* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,					   SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */{	SK_U16	OldRxCmd;	SK_U16	RxCmd;	if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {		GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);		RxCmd = OldRxCmd;		if ((Mode & SK_STRIP_FCS_ON) != 0) {			RxCmd |= GM_RXCR_CRC_DIS;		}		else {			RxCmd &= ~GM_RXCR_CRC_DIS;		}		/* Write the new mode to the Rx control register if required */		if (OldRxCmd != RxCmd) {			GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);		}	}