break;	case SK_LMODE_STAT_UNKNOWN:	default:		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E007, SKERR_HWI_E007MSG);		break;	}}	/* SkXmInitDupMd *//****************************************************************************** * *	SkXmInitPauseMd() - initialize the Pause Mode to be used for this port * * Description: *	This function initializes the Pause Mode which should *	be used for this port. *	It should be called after successfully finishing *	the Auto-negotiation Process * * Returns: *	nothing */void SkXmInitPauseMd(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Port)		/* Port Index (MAC_1 + n) */{	SK_GEPORT	*pPrt;	SK_U32		DWord;	SK_U16		Word;	pPrt = &pAC->GIni.GP[Port];	XM_IN16(IoC, Port, XM_MMU_CMD, &Word);	if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||		pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {		/* Disable Pause Frame Reception */		Word |= XM_MMU_IGN_PF;	}	else {		/*		 * enabling pause frame reception is required for 1000BT		 * because the XMAC is not reset if the link is going down		 */		/* Enable Pause Frame Reception */		Word &= ~XM_MMU_IGN_PF;	}	XM_OUT16(IoC, Port, XM_MMU_CMD, Word);	XM_IN32(IoC, Port, XM_MODE, &DWord);	if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_SYMMETRIC ||		pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {		/*		 * Configure Pause Frame Generation		 * Use internal and external Pause Frame Generation.		 * Sending pause frames is edge triggered.		 * Send a Pause frame with the maximum pause time if		 * internal oder external FIFO full condition occurs.		 * Send a zero pause time frame to re-start transmission.		 */		/* XM_PAUSE_DA = '010000C28001' (default) */		/* XM_MAC_PTIME = 0xffff (maximum) */		/* remember this value is defined in big endian (!) */		XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);		/* Set Pause Mode in Mode Register */		DWord |= XM_PAUSE_MODE;		/* Set Pause Mode in MAC Rx FIFO */		SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE);	}	else {		/*		 * disable pause frame generation is required for 1000BT		 * because the XMAC is not reset if the link is going down		 */		/* Disable Pause Mode in Mode Register */		DWord &= ~XM_PAUSE_MODE;		/* Disable Pause Mode in MAC Rx FIFO */		SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);	}	XM_OUT32(IoC, Port, XM_MODE, DWord);}	/* SkXmInitPauseMd*//****************************************************************************** * *	SkXmInitPhyXmac() - Initialize the XMAC Phy registers * * Description:	initializes all the XMACs Phy registers * * Note: * * Returns: *	nothing */static void SkXmInitPhyXmac(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Port,		/* Port Index (MAC_1 + n) */SK_BOOL	DoLoop)		/* Should a Phy LoopBack be set-up? */{	SK_GEPORT	*pPrt;	SK_U16		Ctrl;	pPrt = &pAC->GIni.GP[Port];	Ctrl = 0;	/* Auto-negotiation ? */	if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("InitPhyXmac: no auto-negotiation Port %d\n", Port));		/* Set DuplexMode in Config register */		if (pPrt->PLinkMode == SK_LMODE_FULL) {			Ctrl |= PHY_CT_DUP_MD;		}		/*		 * Do NOT enable Auto-negotiation here. This would hold		 * the link down because no IDLEs are transmitted		 */	}	else {		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("InitPhyXmac: with auto-negotiation Port %d\n", Port));		/* Set Auto-negotiation advertisement */		/* Set Full/half duplex capabilities */		switch (pPrt->PLinkMode) {		case SK_LMODE_AUTOHALF:			Ctrl |= PHY_X_AN_HD;			break;		case SK_LMODE_AUTOFULL:			Ctrl |= PHY_X_AN_FD;			break;		case SK_LMODE_AUTOBOTH:			Ctrl |= PHY_X_AN_FD | PHY_X_AN_HD;			break;		default:			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,				SKERR_HWI_E015MSG);		}		switch (pPrt->PFlowCtrlMode) {		case SK_FLOW_MODE_NONE:			Ctrl |= PHY_X_P_NO_PAUSE;			break;		case SK_FLOW_MODE_LOC_SEND:			Ctrl |= PHY_X_P_ASYM_MD;			break;		case SK_FLOW_MODE_SYMMETRIC:			Ctrl |= PHY_X_P_SYM_MD;			break;		case SK_FLOW_MODE_SYM_OR_REM:			Ctrl |= PHY_X_P_BOTH_MD;			break;		default:			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,				SKERR_HWI_E016MSG);		}		/* Write AutoNeg Advertisement Register */		SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_AUNE_ADV, Ctrl);		/* Restart Auto-negotiation */		Ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;	}	if (DoLoop) {		/* Set the Phy Loopback bit, too */		Ctrl |= PHY_CT_LOOP;	}	/* Write to the Phy control register */	SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl);}	/* SkXmInitPhyXmac *//****************************************************************************** * *	SkXmInitPhyBcom() - Initialize the Broadcom Phy registers * * Description:	initializes all the Broadcom Phy registers * * Note: * * Returns: *	nothing */static void SkXmInitPhyBcom(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Port,		/* Port Index (MAC_1 + n) */SK_BOOL	DoLoop)		/* Should a Phy LoopBack be set-up? */{	SK_GEPORT	*pPrt;	SK_U16		Ctrl1;	SK_U16		Ctrl2;	SK_U16		Ctrl3;	SK_U16		Ctrl4;	SK_U16		Ctrl5;	Ctrl1 = PHY_CT_SP1000;	Ctrl2 = 0;	Ctrl3 = PHY_SEL_TYPE;	Ctrl4 = PHY_B_PEC_EN_LTR;	Ctrl5 = PHY_B_AC_TX_TST;	pPrt = &pAC->GIni.GP[Port];	/* manually Master/Slave ? */	if (pPrt->PMSMode != SK_MS_MODE_AUTO) {		Ctrl2 |= PHY_B_1000C_MSE;		if (pPrt->PMSMode == SK_MS_MODE_MASTER) {			Ctrl2 |= PHY_B_1000C_MSC;		}	}	/* Auto-negotiation ? */	if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("InitPhyBcom: no auto-negotiation Port %d\n", Port));		/* Set DuplexMode in Config register */		Ctrl1 |= (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0);		/* Determine Master/Slave manually if not already done */		if (pPrt->PMSMode == SK_MS_MODE_AUTO) {			Ctrl2 |= PHY_B_1000C_MSE;	/* set it to Slave */		}		/*		 * Do NOT enable Auto-negotiation here. This would hold		 * the link down because no IDLES are transmitted		 */	}	else {		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("InitPhyBcom: with auto-negotiation Port %d\n", Port));		/* Set Auto-negotiation advertisement */		/*		 * Workaround BCOM Errata #1 for the C5 type.		 * 1000Base-T Link Acquisition Failure in Slave Mode		 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register		 */		Ctrl2 |= PHY_B_1000C_RD;		 /* Set Full/half duplex capabilities */		switch (pPrt->PLinkMode) {		case SK_LMODE_AUTOHALF:			Ctrl2 |= PHY_B_1000C_AHD;			break;		case SK_LMODE_AUTOFULL:			Ctrl2 |= PHY_B_1000C_AFD;			break;		case SK_LMODE_AUTOBOTH:			Ctrl2 |= PHY_B_1000C_AFD | PHY_B_1000C_AHD;			break;		default:			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,				SKERR_HWI_E015MSG);		}		switch (pPrt->PFlowCtrlMode) {		case SK_FLOW_MODE_NONE:			Ctrl3 |= PHY_B_P_NO_PAUSE;			break;		case SK_FLOW_MODE_LOC_SEND:			Ctrl3 |= PHY_B_P_ASYM_MD;			break;		case SK_FLOW_MODE_SYMMETRIC:			Ctrl3 |= PHY_B_P_SYM_MD;			break;		case SK_FLOW_MODE_SYM_OR_REM:			Ctrl3 |= PHY_B_P_BOTH_MD;			break;		default:			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,				SKERR_HWI_E016MSG);		}		/* Restart Auto-negotiation */		Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;	}	/* Initialize LED register here? */	/* No. Please do it in SkDgXmitLed() (if required) and swap	   init order of LEDs and XMAC. (MAl) */	/* Write 1000Base-T Control Register */	SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,		("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));	/* Write AutoNeg Advertisement Register */	SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,		("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3));	if (DoLoop) {		/* Set the Phy Loopback bit, too */		Ctrl1 |= PHY_CT_LOOP;	}	if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {		/* configure FIFO to high latency for transmission of ext. packets */		Ctrl4 |= PHY_B_PEC_HIGH_LA;		/* configure reception of extended packets */		Ctrl5 |= PHY_B_AC_LONG_PACK;		SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, Ctrl5);	}	/* Configure LED Traffic Mode and Jumbo Frame usage if specified */	SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);	/* Write to the Phy control register */	SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,		("PHY Control Reg=0x%04X\n", Ctrl1));}	/* SkXmInitPhyBcom *//****************************************************************************** * *	SkGmInitPhyMarv() - Initialize the Marvell Phy registers * * Description:	initializes all the Marvell Phy registers * * Note: * * Returns: *	nothing */static void SkGmInitPhyMarv(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Port,		/* Port Index (MAC_1 + n) */SK_BOOL	DoLoop)		/* Should a Phy LoopBack be set-up? */{	SK_GEPORT	*pPrt;	SK_U16		PhyCtrl;	SK_U16		C1000BaseT;	SK_U16		AutoNegAdv;	SK_U16		ExtPhyCtrl;	SK_U16		PhyStat;	SK_U16		PhyStat1;	SK_U16		PhySpecStat;	SK_U16		LedCtrl;	SK_BOOL		AutoNeg;#ifdef VCPU	VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",		Port, DoLoop);#else /* VCPU */	pPrt = &pAC->GIni.GP[Port];	/* Auto-negotiation ? */	if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {		AutoNeg = SK_FALSE;	}	else {		AutoNeg = SK_TRUE;	}	if (!DoLoop) {		/* Read Ext. PHY Specific Control */		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);		ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |			PHY_M_EC_MAC_S_MSK);		ExtPhyCtrl |= PHY_M_EC_M_DSC(1) | PHY_M_EC_S_DSC(1) |			PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("Ext.PHYCtrl=0x%04X\n", ExtPhyCtrl));		/* Read PHY Control */		SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);		/* Assert software reset */		SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL,			(SK_U16)(PhyCtrl | PHY_CT_RESET));	}#endif /* VCPU */	PhyCtrl = 0 /* PHY_CT_COL_TST */;	C1000BaseT = 0;	AutoNegAdv = PHY_SEL_TYPE;	/* manually Master/Slave ? */	if (pPrt->PMSMode != SK_MS_MODE_AUTO) {		/* enable Manual Master/Slave */		C1000BaseT |= PHY_M_1000C_MSE;		if (pPrt->PMSMode == SK_MS_MODE_MASTER) {			C1000BaseT |= PHY_M_1000C_MSC;	/* set it to Master */		}	}	/* Auto-negotiation ? */	if (!AutoNeg) {		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("InitPhyMarv: no auto-negotiation Port %d\n", Port));		if (pPrt->PLinkMode == SK_LMODE_FULL) {			/* Set Full Duplex Mode */			PhyCtrl |= PHY_CT_DUP_MD;		}		/* Set Master/Slave manually if not already done */		if (pPrt->PMSMode == SK_MS_MODE_AUTO) {			C1000BaseT |= PHY_M_1000C_MSE;	/* set it to Slave */		}		/* Set Speed */		switch (pPrt->PLinkSpeed) {		case SK_LSPEED_AUTO:		case SK_LSPEED_1000MBPS:			PhyCtrl |= PHY_CT_SP1000;			break;		case SK_LSPEED_100MBPS:			PhyCtrl |= PHY_CT_SP100;			break;		case SK_LSPEED_10MBPS:			break;		default:			SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,				SKERR_HWI_E019MSG);		}		if (!DoLoop) {			PhyCtrl |= PHY_CT_RESET;		}		/*		 * Do NOT enable Auto-negotiation here. This would hold		 * the link down because no IDLES are transmitted		 */	}	else {		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,			("InitPhyMarv: with auto-negotiation Port %d\n", Port));		PhyCtrl |= PHY_CT_ANE;		if (pAC->GIni.GICopperType) {			/* Set Speed capabilities */			switch (pPrt->PLinkSpeed) {			case SK_LSPEED_AUTO:				C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;				AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |					PHY_M_AN_10_FD | PHY_M_AN_10_HD;				break;			case SK_LSPEED_1000MBPS:				C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;				break;			case SK_LSPEED_100MBPS:				AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |					PHY_M_AN_10_FD | PHY_M_AN_10_HD;				break;			case SK_LSPEED_10MBPS:				AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;				break;			default:				SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,					SKERR_HWI_E019MSG);			}			/* Set Full/half duplex