#define B2_IRQM_VAL		0x0144	/* 32 bit	IRQ Moderation Timer Value */#define B2_IRQM_CTRL	0x0148	/*  8 bit	IRQ Moderation Timer Control */#define B2_IRQM_TEST	0x0149	/*  8 bit	IRQ Moderation Timer Test */#define B2_IRQM_MSK 	0x014c	/* 32 bit	IRQ Moderation Mask */#define B2_IRQM_HWE_MSK 0x0150	/* 32 bit	IRQ Moderation HW Error Mask */	/* 0x0154 - 0x0157:	reserved */#define B2_TST_CTRL1	0x0158	/*  8 bit	Test Control Register 1 */#define B2_TST_CTRL2	0x0159	/*  8 bit	Test Control Register 2 */	/* 0x015a - 0x015b:	reserved */#define B2_GP_IO		0x015c	/* 32 bit	General Purpose I/O Register */#define B2_I2C_CTRL		0x0160	/* 32 bit	I2C HW Control Register */#define B2_I2C_DATA		0x0164	/* 32 bit	I2C HW Data Register */#define B2_I2C_IRQ		0x0168	/* 32 bit	I2C HW IRQ Register */#define B2_I2C_SW		0x016c	/* 32 bit	I2C SW Port Register *//* Blink Source Counter (GENESIS only) */#define B2_BSC_INI		0x0170	/* 32 bit	Blink Source Counter Init Val */#define B2_BSC_VAL		0x0174	/* 32 bit	Blink Source Counter Value */#define B2_BSC_CTRL		0x0178	/*  8 bit	Blink Source Counter Control */#define B2_BSC_STAT		0x0179	/*  8 bit	Blink Source Counter Status */#define B2_BSC_TST		0x017a	/* 16 bit	Blink Source Counter Test Reg */	/* 0x017c - 0x017f:	reserved *//* *	Bank 3 *//* RAM Random Registers */#define B3_RAM_ADDR		0x0180	/* 32 bit	RAM Address, to read or write */#define B3_RAM_DATA_LO	0x0184	/* 32 bit	RAM Data Word (low dWord) */#define B3_RAM_DATA_HI	0x0188	/* 32 bit	RAM Data Word (high dWord) */	/* 0x018c - 0x018f:	reserved *//* RAM Interface Registers *//* * The HW-Spec. calls this registers Timeout Value 0..11. But this names are * not usable in SW. Please notice these are NOT real timeouts, these are * the number of qWords transferred continuously. */#define B3_RI_WTO_R1	0x0190	/*  8 bit	WR Timeout Queue R1		(TO0) */#define B3_RI_WTO_XA1	0x0191	/*  8 bit	WR Timeout Queue XA1	(TO1) */#define B3_RI_WTO_XS1	0x0192	/*  8 bit	WR Timeout Queue XS1	(TO2) */#define B3_RI_RTO_R1	0x0193	/*  8 bit	RD Timeout Queue R1		(TO3) */#define B3_RI_RTO_XA1	0x0194	/*  8 bit	RD Timeout Queue XA1	(TO4) */#define B3_RI_RTO_XS1	0x0195	/*  8 bit	RD Timeout Queue XS1	(TO5) */#define B3_RI_WTO_R2	0x0196	/*  8 bit	WR Timeout Queue R2		(TO6) */#define B3_RI_WTO_XA2	0x0197	/*  8 bit	WR Timeout Queue XA2	(TO7) */#define B3_RI_WTO_XS2	0x0198	/*  8 bit	WR Timeout Queue XS2	(TO8) */#define B3_RI_RTO_R2	0x0199	/*  8 bit	RD Timeout Queue R2		(TO9) */#define B3_RI_RTO_XA2	0x019a	/*  8 bit	RD Timeout Queue XA2	(TO10)*/#define B3_RI_RTO_XS2	0x019b	/*  8 bit	RD Timeout Queue XS2	(TO11)*/#define B3_RI_TO_VAL	0x019c	/*  8 bit	Current Timeout Count Val */	/* 0x019d - 0x019f:	reserved */#define B3_RI_CTRL		0x01a0	/* 16 bit	RAM Interface Control Register */#define B3_RI_TEST		0x01a2	/*  8 bit	RAM Interface Test Register */	/* 0x01a3 - 0x01af:	reserved *//* MAC Arbiter Registers (GENESIS only) *//* these are the no. of qWord transferred continuously and NOT real timeouts */#define B3_MA_TOINI_RX1	0x01b0	/*  8 bit	Timeout Init Val Rx Path MAC 1 */#define B3_MA_TOINI_RX2	0x01b1	/*  8 bit	Timeout Init Val Rx Path MAC 2 */#define B3_MA_TOINI_TX1	0x01b2	/*  8 bit	Timeout Init Val Tx Path MAC 1 */#define B3_MA_TOINI_TX2	0x01b3	/*  8 bit	Timeout Init Val Tx Path MAC 2 */#define B3_MA_TOVAL_RX1	0x01b4	/*  8 bit	Timeout Value Rx Path MAC 1 */#define B3_MA_TOVAL_RX2	0x01b5	/*  8 bit	Timeout Value Rx Path MAC 1 */#define B3_MA_TOVAL_TX1	0x01b6	/*  8 bit	Timeout Value Tx Path MAC 2 */#define B3_MA_TOVAL_TX2	0x01b7	/*  8 bit	Timeout Value Tx Path MAC 2 */#define B3_MA_TO_CTRL	0x01b8	/* 16 bit	MAC Arbiter Timeout Ctrl Reg */#define B3_MA_TO_TEST	0x01ba	/* 16 bit	MAC Arbiter Timeout Test Reg */	/* 0x01bc - 0x01bf:	reserved */#define B3_MA_RCINI_RX1	0x01c0	/*  8 bit	Recovery Init Val Rx Path MAC 1 */#define B3_MA_RCINI_RX2	0x01c1	/*  8 bit	Recovery Init Val Rx Path MAC 2 */#define B3_MA_RCINI_TX1	0x01c2	/*  8 bit	Recovery Init Val Tx Path MAC 1 */#define B3_MA_RCINI_TX2	0x01c3	/*  8 bit	Recovery Init Val Tx Path MAC 2 */#define B3_MA_RCVAL_RX1	0x01c4	/*  8 bit	Recovery Value Rx Path MAC 1 */#define B3_MA_RCVAL_RX2	0x01c5	/*  8 bit	Recovery Value Rx Path MAC 1 */#define B3_MA_RCVAL_TX1	0x01c6	/*  8 bit	Recovery Value Tx Path MAC 2 */#define B3_MA_RCVAL_TX2	0x01c7	/*  8 bit	Recovery Value Tx Path MAC 2 */#define B3_MA_RC_CTRL	0x01c8	/* 16 bit	MAC Arbiter Recovery Ctrl Reg */#define B3_MA_RC_TEST	0x01ca	/* 16 bit	MAC Arbiter Recovery Test Reg */	/* 0x01cc - 0x01cf:	reserved *//* Packet Arbiter Registers (GENESIS only) *//* these are real timeouts */#define B3_PA_TOINI_RX1	0x01d0	/* 16 bit	Timeout Init Val Rx Path MAC 1 */	/* 0x01d2 - 0x01d3:	reserved */#define B3_PA_TOINI_RX2	0x01d4	/* 16 bit	Timeout Init Val Rx Path MAC 2 */	/* 0x01d6 - 0x01d7:	reserved */#define B3_PA_TOINI_TX1	0x01d8	/* 16 bit	Timeout Init Val Tx Path MAC 1 */	/* 0x01da - 0x01db:	reserved */#define B3_PA_TOINI_TX2	0x01dc	/* 16 bit	Timeout Init Val Tx Path MAC 2 */	/* 0x01de - 0x01df:	reserved */#define B3_PA_TOVAL_RX1	0x01e0	/* 16 bit	Timeout Val Rx Path MAC 1 */	/* 0x01e2 - 0x01e3:	reserved */#define B3_PA_TOVAL_RX2	0x01e4	/* 16 bit	Timeout Val Rx Path MAC 2 */	/* 0x01e6 - 0x01e7:	reserved */#define B3_PA_TOVAL_TX1	0x01e8	/* 16 bit	Timeout Val Tx Path MAC 1 */	/* 0x01ea - 0x01eb:	reserved */#define B3_PA_TOVAL_TX2	0x01ec	/* 16 bit	Timeout Val Tx Path MAC 2 */	/* 0x01ee - 0x01ef:	reserved */#define B3_PA_CTRL	0x01f0	/* 16 bit	Packet Arbiter Ctrl Register */#define B3_PA_TEST	0x01f2	/* 16 bit	Packet Arbiter Test Register */	/* 0x01f4 - 0x01ff:	reserved *//* *	Bank 4 - 5 *//* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */#define TXA_ITI_INI		0x0200	/* 32 bit	Tx Arb Interval Timer Init Val*/#define TXA_ITI_VAL		0x0204	/* 32 bit	Tx Arb Interval Timer Value */#define TXA_LIM_INI		0x0208	/* 32 bit	Tx Arb Limit Counter Init Val */#define TXA_LIM_VAL		0x020c	/* 32 bit	Tx Arb Limit Counter Value */#define TXA_CTRL		0x0210	/*  8 bit	Tx Arbiter Control Register */#define TXA_TEST		0x0211	/*  8 bit	Tx Arbiter Test Register */#define TXA_STAT		0x0212	/*  8 bit	Tx Arbiter Status Register */	/* 0x0213 - 0x027f:	reserved */	/* 0x0280 - 0x0292:	MAC 2 */	/* 0x0213 - 0x027f:	reserved *//* *	Bank 6 *//* External registers (GENESIS only) */#define B6_EXT_REG		0x0300/* *	Bank 7 *//* This is a copy of the Configuration register file (lower half) */#define B7_CFG_SPC		0x0380/* *	Bank 8 - 15 *//* Receive and Transmit Queue Registers, use Q_ADDR() to access */#define B8_Q_REGS		0x0400/* Queue Register Offsets, use Q_ADDR() to access */#define Q_D		0x00	/* 8*32	bit	Current Descriptor */#define Q_DA_L	0x20	/* 32 bit	Current Descriptor Address Low dWord */#define Q_DA_H	0x24	/* 32 bit	Current Descriptor Address High dWord */#define Q_AC_L	0x28	/* 32 bit	Current Address Counter Low dWord */#define Q_AC_H	0x2c	/* 32 bit	Current Address Counter High dWord */#define Q_BC	0x30	/* 32 bit	Current Byte Counter */#define Q_CSR	0x34	/* 32 bit	BMU Control/Status Register */#define Q_F		0x38	/* 32 bit	Flag Register */#define Q_T1	0x3c	/* 32 bit	Test Register 1 */#define Q_T1_TR	0x3c	/*  8 bit	Test Register 1 Transfer SM */#define Q_T1_WR	0x3d	/*  8 bit	Test Register 1 Write Descriptor SM */#define Q_T1_RD	0x3e	/*  8 bit	Test Register 1 Read Descriptor SM */#define Q_T1_SV	0x3f	/*  8 bit	Test Register 1 Supervisor SM */#define Q_T2	0x40	/* 32 bit	Test Register 2	*/#define Q_T3	0x44	/* 32 bit	Test Register 3	*/	/* 0x48 - 0x7f:	reserved *//* *	Bank 16 - 23 *//* RAM Buffer Registers */#define B16_RAM_REGS	0x0800/* RAM Buffer Register Offsets, use RB_ADDR() to access */#define RB_START		0x00	/* 32 bit	RAM Buffer Start Address */#define RB_END			0x04	/* 32 bit	RAM Buffer End Address */#define RB_WP			0x08	/* 32 bit	RAM Buffer Write Pointer */#define RB_RP			0x0c	/* 32 bit	RAM Buffer Read Pointer */#define RB_RX_UTPP		0x10	/* 32 bit	Rx Upper Threshold, Pause Pack */#define RB_RX_LTPP		0x14	/* 32 bit	Rx Lower Threshold, Pause Pack */#define RB_RX_UTHP		0x18	/* 32 bit	Rx Upper Threshold, High Prio */#define RB_RX_LTHP		0x1c	/* 32 bit	Rx Lower Threshold, High Prio */	/* 0x10 - 0x1f:	reserved at Tx RAM Buffer Registers */#define RB_PC			0x20	/* 32 bit	RAM Buffer Packet Counter */#define RB_LEV			0x24	/* 32 bit	RAM Buffer Level Register */#define RB_CTRL			0x28	/*  8 bit	RAM Buffer Control Register */#define RB_TST1			0x29	/*  8 bit	RAM Buffer Test Register 1 */#define RB_TST2			0x2A	/*  8 bit	RAM Buffer Test Register 2 */	/* 0x2c - 0x7f:	reserved *//* *	Bank 24 *//* * Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) * use MR_ADDR() to access */#define RX_MFF_EA		0x0c00	/* 32 bit	Receive MAC FIFO End Address */#define RX_MFF_WP		0x0c04	/* 32 bit 	Receive MAC FIFO Write Pointer */	/* 0x0c08 - 0x0c0b:	reserved */#define RX_MFF_RP		0x0c0c	/* 32 bit	Receive MAC FIFO Read Pointer */#define RX_MFF_PC		0x0c10	/* 32 bit	Receive MAC FIFO Packet Cnt */#define RX_MFF_LEV		0x0c14	/* 32 bit	Receive MAC FIFO Level */#define RX_MFF_CTRL1	0x0c18	/* 16 bit	Receive MAC FIFO Control Reg 1*/#define RX_MFF_STAT_TO	0x0c1a	/*  8 bit	Receive MAC Status Timeout */#define RX_MFF_TIST_TO	0x0c1b	/*  8 bit	Receive MAC Time Stamp Timeout */#define RX_MFF_CTRL2	0x0c1c	/*  8 bit	Receive MAC FIFO Control Reg 2*/#define RX_MFF_TST1		0x0c1d	/*  8 bit	Receive MAC FIFO Test Reg 1 */#define RX_MFF_TST2		0x0c1e	/*  8 bit	Receive MAC FIFO Test Reg 2 */	/* 0x0c1f:	reserved */#define RX_LED_INI		0x0c20	/* 32 bit	Receive LED Cnt Init Value */#define RX_LED_VAL		0x0c24	/* 32 bit	Receive LED Cnt Current Value */#define RX_LED_CTRL		0x0c28	/*  8 bit	Receive LED Cnt Control Reg */#define RX_LED_TST		0x0c29	/*  8 bit	Receive LED Cnt Test Register */	/* 0x0c2a - 0x0c2f:	reserved */#define LNK_SYNC_INI	0x0c30	/* 32 bit	Link Sync Cnt Init Value */#define LNK_SYNC_VAL	0x0c34	/* 32 bit	Link Sync Cnt Current Value */#define LNK_SYNC_CTRL	0x0c38	/*  8 bit	Link Sync Cnt Control Register */#define LNK_SYNC_TST	0x0c39	/*  8 bit	Link Sync Cnt Test Register */	/* 0x0c3a - 0x0c3b:	reserved */#define LNK_LED_REG		0x0c3c	/*  8 bit	Link LED Register */	/* 0x0c3d - 0x0c3f:	reserved *//* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */#define RX_GMF_EA		0x0c40	/* 32 bit	Rx GMAC FIFO End Address */#define RX_GMF_AF_THR	0x0c44	/* 32 bit	Rx GMAC FIFO Almost Full Thresh. */#define RX_GMF_CTRL_T	0x0c48	/* 32 bit	Rx GMAC FIFO Control/Test */#define RX_GMF_FL_MSK	0x0c4c	/* 32 bit	Rx GMAC FIFO Flush Mask */#define RX_GMF_FL_THR	0x0c50	/* 32 bit	Rx GMAC FIFO Flush Threshold */	/* 0x0c54 - 0x0c5f:	reserved */#define RX_GMF_WP		0x0c60	/* 32 bit 	Rx GMAC FIFO Write Pointer */	/* 0x0c64 - 0x0c67:	reserved */#define RX_GMF_WLEV		0x0c68	/* 32 bit 	Rx GMAC FIFO Write Level */	/* 0x0c6c - 0x0c6f:	reserved */#define RX_GMF_RP		0x0c70	/* 32 bit 	Rx GMAC FIFO Read Pointer */	/* 0x0c74 - 0x0c77:	reserved */#define RX_GMF_RLEV		0x0c78	/* 32 bit 	Rx GMAC FIFO Read Level */	/* 0x0c7c - 0x0c7f:	reserved *//* *	Bank 25 */	/* 0x0c80 - 0x0cbf:	MAC 2 */	/* 0x0cc0 - 0x0cff:	reserved *//* *	Bank 26 *//* * Transmit MAC FIFO and Transmit LED Registers (GENESIS only), * use MR_ADDR() to access */#define TX_MFF_EA		0x0d00	/* 32 bit	Transmit MAC FIFO End Address */#define TX_MFF_WP		0x0d04	/* 32 bit 	Transmit MAC FIFO WR Pointer */#define TX_MFF_WSP		0x0d08	/* 32 bit	Transmit MAC FIFO WR Shadow Ptr */#define TX_MFF_RP		0x0d0c	/* 32 bit	Transmit MAC FIFO RD Pointer */#define TX_MFF_PC		0x0d10	/* 32 bit	Transmit MAC FIFO Packet Cnt */#define TX_MFF_LEV		0x0d14	/* 32 bit	Transmit MAC FIFO Level */#define TX_MFF_CTRL1	0x0d18	/* 16 bit	Transmit MAC FIFO Ctrl Reg 1 */#define TX_MFF_WAF		0x0d1a	/*  8 bit	Transmit MAC Wait after flush */	/* 0x0c1b:	reserved */#define TX_MFF_CTRL2	0x0d1c	/*  8 bit	Transmit MAC FIFO Ctrl Reg 2 */#define TX_MFF_TST1		0x0d1d	/*  8 bit	Transmit MAC FIFO Test Reg 1 */#define TX_MFF_TST2		0x0d1e	/*  8 bit	Transmit MAC FIFO Test Reg 2 */	/* 0x0d1f:	reserved */#define TX_LED_INI		0x0d20	/* 32 bit	Transmit LED Cnt Init Value */#define TX_LED_VAL		0x0d24	/* 32 bit	Transmit LED Cnt Current Val */#define TX_LED_CTRL		0x0d28	/*  8 bit	Transmit LED Cnt Control Reg */#define TX_LED_TST		0x0d29	/*  8 bit	Transmit LED Cnt Test Reg */	/* 0x0d2a - 0x0d3f:	reserved *//* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */#define TX_GMF_EA		0x0d40	/* 32 bit	Tx GMAC FIFO End Address */#define TX_GMF_AE_THR	0x0d44	/* 32 bit	Tx GMAC FIFO Almost Empty Thresh.*/#define TX_GMF_CTRL_T	0x0d48	/* 32 bit	Tx GMAC FIFO Control/Test */	/* 0x0d4c - 0x0d5f:	reserved */#define TX_GMF_WP		0x0d60	/* 32 bit 	Tx GMAC FIFO Write Pointer */#define TX_GMF_WSP		0x0d64	/* 32 bit 	Tx GMAC FIFO Write Shadow Ptr. */#define TX_GMF_WLEV		0x0d68	/* 32 bit 	Tx GMAC FIFO Write Level */	/* 0x0d6c - 0x0d6f:	reserved */#define TX_GMF_RP		0x0d70	/* 32 bit 	Tx GMAC FIFO Read Pointer */#define TX_GMF_RSTP		0x0d74	/* 32 bit 	Tx GMAC FIFO Restart Pointer */#define TX_GMF_RLEV		0x0d78	/* 32 bit 	Tx GMAC FIFO Read Level */	/* 0x0d7c - 0x0d7f:	reserved *//* *	Bank 27 */	/* 0x0d80 - 0x0dbf:	MAC 2 */	/* 0x0daa - 0x0dff:	reserved *//* *	Bank 28 *//* Descriptor Poll Timer Registers */#define B28_DPT_INI		0x0e00	/* 24 bit	Descriptor Poll Timer Init Val */#define B28_DPT_VAL		0x0e04	/* 24 bit	Descriptor Poll Timer Curr Val */#define B28_DPT_CTRL	0x0e08	/*  8 bit	Descriptor Poll Timer Ctrl Reg */	/* 0x0e09:	reserved */#define B28_DPT_TST		0x0e0a	/*  8 bit	Descriptor Poll Timer Test Reg */	/* 0x0e0b:	reserved *//* Time Stamp Timer Registers (YUKON only) */	/* 0x0e10:	reserved */#define GMAC_TI_ST_VAL	0x0e14	/* 32 bit	Time Stamp Timer Curr Val */#define GMAC_TI_ST_CTRL	0x0e18	/*  8 bit	Time Stamp Timer Ctrl Reg */	/* 0x0e19:	reserved */#define GMAC_TI_ST_TST	0x0e1a	/*  8 bit	Time Stamp Timer Test Reg */	/* 0x0e1b - 0x0e7f:	reserved *//* *	Bank 29 */	/* 0x0e80 - 0x0efc:	reserved *//* *	Bank 30 *//* GMAC and GPHY Control Registers (YUKON only) */#define GMAC_CTRL		0x0f00	/* 32 bit	GMAC Control Reg */#define GPHY_CTRL		0x0f04	/* 32 bit	GPHY Control Reg */#define GMAC_IRQ_SRC	0x0f08	/*  8 bit	GMAC Interrupt Source Reg */	/* 0x0f09 - 0x0f0b:	reserved */#define GMAC_IRQ_MSK	0x0f0c	/*  8 bit	GMAC Interrupt Mask Reg */