/* 0x0f0d - 0x0f0f:	reserved */#define GMAC_LINK_CTRL	0x0f10	/* 16 bit	Link Control Reg */	/* 0x0f14 - 0x0f1f:	reserved *//* Wake-up Frame Pattern Match Control Registers (YUKON only) */#define WOL_REG_OFFS	0x20	/* HW-Bug: Address is + 0x20 against spec. */#define WOL_CTRL_STAT	0x0f20	/* 16 bit	WOL Control/Status Reg */#define WOL_MATCH_CTL	0x0f22	/*  8 bit	WOL Match Control Reg */#define WOL_MATCH_RES	0x0f23	/*  8 bit	WOL Match Result Reg */#define WOL_MAC_ADDR_LO	0x0f24	/* 32 bit	WOL MAC Address Low */#define WOL_MAC_ADDR_HI	0x0f28	/* 16 bit	WOL MAC Address High */#define WOL_PATT_RPTR	0x0f2c	/*  8 bit	WOL Pattern Read Ptr *//* use this macro to access above registers */#define WOL_REG(Reg)	((Reg) + (pAC->GIni.GIWolOffs))/* WOL Pattern Length Registers (YUKON only) */#define WOL_PATT_LEN_LO	0x0f30		/* 32 bit	WOL Pattern Length 3..0 */#define WOL_PATT_LEN_HI	0x0f34		/* 24 bit	WOL Pattern Length 6..4 *//* WOL Pattern Counter Registers (YUKON only) */#define WOL_PATT_CNT_0	0x0f38		/* 32 bit	WOL Pattern Counter 3..0 */#define WOL_PATT_CNT_4	0x0f3c		/* 24 bit	WOL Pattern Counter 6..4 */	/* 0x0f40 - 0x0f7f:	reserved *//* *	Bank 31 *//* 0x0f80 - 0x0fff:	reserved *//* *	Bank 32	- 33 */#define WOL_PATT_RAM_1	0x1000	/*  WOL Pattern RAM Link 1 *//* *	Bank 0x22 - 0x3f *//* 0x1100 - 0x1fff:	reserved *//* *	Bank 0x40 - 0x4f */#define BASE_XMAC_1		0x2000	/* XMAC 1 registers *//* *	Bank 0x50 - 0x5f */#define BASE_GMAC_1		0x2800	/* GMAC 1 registers *//* *	Bank 0x60 - 0x6f */#define BASE_XMAC_2		0x3000	/* XMAC 2 registers *//* *	Bank 0x70 - 0x7f */#define BASE_GMAC_2		0x3800	/* GMAC 2 registers *//* *	Control Register Bit Definitions: *//*	B0_RAP		8 bit	Register Address Port */								/* Bit 7:	reserved */#define RAP_RAP			0x3f	/* Bit 6..0:	0 = block 0,..,6f = block 6f *//*	B0_CTST		16 bit	Control/Status register */								/* Bit 15..14:	reserved */#define CS_CLK_RUN_HOT	BIT_13S		/* CLK_RUN hot m. (YUKON-Lite only) */#define CS_CLK_RUN_RST	BIT_12S		/* CLK_RUN reset  (YUKON-Lite only) */#define CS_CLK_RUN_ENA	BIT_11S		/* CLK_RUN enable (YUKON-Lite only) */#define CS_VAUX_AVAIL	BIT_10S		/* VAUX available (YUKON only) */#define CS_BUS_CLOCK	BIT_9S		/* Bus Clock 0/1 = 33/66 MHz */#define CS_BUS_SLOT_SZ	BIT_8S		/* Slot Size 0/1 = 32/64 bit slot */#define CS_ST_SW_IRQ	BIT_7S		/* Set IRQ SW Request */#define CS_CL_SW_IRQ	BIT_6S		/* Clear IRQ SW Request */#define CS_STOP_DONE	BIT_5S		/* Stop Master is finished */#define CS_STOP_MAST	BIT_4S		/* Command Bit to stop the master */#define CS_MRST_CLR		BIT_3S		/* Clear Master reset	*/#define CS_MRST_SET		BIT_2S		/* Set Master reset	*/#define CS_RST_CLR		BIT_1S		/* Clear Software reset	*/#define CS_RST_SET		BIT_0S		/* Set   Software reset	*//*	B0_LED		 8 Bit	LED register */								/* Bit  7.. 2:	reserved */#define LED_STAT_ON		BIT_1S		/* Status LED on	*/#define LED_STAT_OFF	BIT_0S		/* Status LED off	*//*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */#define PC_VAUX_ENA		BIT_7		/* Switch VAUX Enable  */#define PC_VAUX_DIS		BIT_6       /* Switch VAUX Disable */#define PC_VCC_ENA		BIT_5       /* Switch VCC Enable  */#define PC_VCC_DIS		BIT_4       /* Switch VCC Disable */#define PC_VAUX_ON		BIT_3       /* Switch VAUX On  */#define PC_VAUX_OFF		BIT_2       /* Switch VAUX Off */#define PC_VCC_ON		BIT_1       /* Switch VCC On  */#define PC_VCC_OFF		BIT_0       /* Switch VCC Off *//*	B0_ISRC		32 bit	Interrupt Source Register *//*	B0_IMSK		32 bit	Interrupt Mask Register *//*	B0_SP_ISRC	32 bit	Special Interrupt Source Reg *//*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */#define IS_ALL_MSK		0xbfffffffL	/* 		All Interrupt bits */#define IS_HW_ERR		BIT_31		/* Interrupt HW Error */								/* Bit 30:	reserved */#define IS_PA_TO_RX1	BIT_29		/* Packet Arb Timeout Rx1 */#define IS_PA_TO_RX2	BIT_28		/* Packet Arb Timeout Rx2 */#define IS_PA_TO_TX1	BIT_27		/* Packet Arb Timeout Tx1 */#define IS_PA_TO_TX2	BIT_26		/* Packet Arb Timeout Tx2 */#define IS_I2C_READY	BIT_25		/* IRQ on end of I2C Tx */#define IS_IRQ_SW		BIT_24		/* SW forced IRQ	*/#define IS_EXT_REG		BIT_23		/* IRQ from LM80 or PHY (GENESIS only) */									/* IRQ from PHY (YUKON only) */#define IS_TIMINT		BIT_22		/* IRQ from Timer	*/#define IS_MAC1			BIT_21		/* IRQ from MAC 1	*/#define IS_LNK_SYNC_M1	BIT_20		/* Link Sync Cnt wrap MAC 1 */#define IS_MAC2			BIT_19		/* IRQ from MAC 2	*/#define IS_LNK_SYNC_M2	BIT_18		/* Link Sync Cnt wrap MAC 2 *//* Receive Queue 1 */#define IS_R1_B			BIT_17		/* Q_R1 End of Buffer */#define IS_R1_F			BIT_16		/* Q_R1 End of Frame */#define IS_R1_C			BIT_15		/* Q_R1 Encoding Error *//* Receive Queue 2 */#define IS_R2_B			BIT_14		/* Q_R2 End of Buffer */#define IS_R2_F			BIT_13		/* Q_R2 End of Frame */#define IS_R2_C			BIT_12		/* Q_R2 Encoding Error *//* Synchronous Transmit Queue 1 */#define IS_XS1_B		BIT_11		/* Q_XS1 End of Buffer */#define IS_XS1_F		BIT_10		/* Q_XS1 End of Frame */#define IS_XS1_C		BIT_9		/* Q_XS1 Encoding Error *//* Asynchronous Transmit Queue 1 */#define IS_XA1_B		BIT_8		/* Q_XA1 End of Buffer */#define IS_XA1_F		BIT_7		/* Q_XA1 End of Frame */#define IS_XA1_C		BIT_6		/* Q_XA1 Encoding Error *//* Synchronous Transmit Queue 2 */#define IS_XS2_B		BIT_5		/* Q_XS2 End of Buffer */#define IS_XS2_F		BIT_4		/* Q_XS2 End of Frame */#define IS_XS2_C		BIT_3		/* Q_XS2 Encoding Error *//* Asynchronous Transmit Queue 2 */#define IS_XA2_B		BIT_2		/* Q_XA2 End of Buffer */#define IS_XA2_F		BIT_1		/* Q_XA2 End of Frame */#define IS_XA2_C		BIT_0		/* Q_XA2 Encoding Error *//*	B0_HWE_ISRC	32 bit	HW Error Interrupt Src Reg *//*	B0_HWE_IMSK	32 bit	HW Error Interrupt Mask Reg *//*	B2_IRQM_HWE_MSK 32 bit	IRQ Moderation HW Error Mask */#define IS_ERR_MSK		0x00000fffL	/* 		All Error bits */								/* Bit 31..14:	reserved */#define IS_IRQ_TIST_OV	BIT_13	/* Time Stamp Timer Overflow (YUKON only) */#define IS_IRQ_SENSOR	BIT_12	/* IRQ from Sensor (YUKON only) */#define IS_IRQ_MST_ERR	BIT_11	/* IRQ master error detected */#define IS_IRQ_STAT		BIT_10	/* IRQ status exception */#define IS_NO_STAT_M1	BIT_9	/* No Rx Status from MAC 1 */#define IS_NO_STAT_M2	BIT_8	/* No Rx Status from MAC 2 */#define IS_NO_TIST_M1	BIT_7	/* No Time Stamp from MAC 1 */#define IS_NO_TIST_M2	BIT_6	/* No Time Stamp from MAC 2 */#define IS_RAM_RD_PAR	BIT_5	/* RAM Read  Parity Error */#define IS_RAM_WR_PAR	BIT_4	/* RAM Write Parity Error */#define IS_M1_PAR_ERR	BIT_3	/* MAC 1 Parity Error */#define IS_M2_PAR_ERR	BIT_2	/* MAC 2 Parity Error */#define IS_R1_PAR_ERR	BIT_1	/* Queue R1 Parity Error */#define IS_R2_PAR_ERR	BIT_0	/* Queue R2 Parity Error *//*	B2_CONN_TYP	 8 bit	Connector type *//*	B2_PMD_TYP	 8 bit	PMD type *//*	Values of connector and PMD type comply to SysKonnect internal std *//*	B2_MAC_CFG	 8 bit	MAC Configuration / Chip Revision */#define CFG_CHIP_R_MSK	(0xf<<4)	/* Bit 7.. 4: Chip Revision */									/* Bit 3.. 2:	reserved */#define CFG_DIS_M2_CLK	BIT_1S		/* Disable Clock for 2nd MAC */#define CFG_SNG_MAC		BIT_0S		/* MAC Config: 0=2 MACs / 1=1 MAC*//*	B2_CHIP_ID	 8 bit 	Chip Identification Number */#define CHIP_ID_GENESIS	0x0a		/* Chip ID for GENESIS */#define CHIP_ID_YUKON	0xb0		/* Chip ID for YUKON *//*	B2_FAR		32 bit	Flash-Prom Addr Reg/Cnt */#define FAR_ADDR		0x1ffffL	/* Bit 16.. 0:	FPROM Address mask *//*	B2_LD_CRTL	 8 bit	EPROM loader control register *//*	Bits are currently reserved *//*	B2_LD_TEST	 8 bit	EPROM loader test register */								/* Bit 7.. 4:	reserved */#define LD_T_ON			BIT_3S	/* Loader Test mode on */#define LD_T_OFF		BIT_2S	/* Loader Test mode off */#define LD_T_STEP		BIT_1S	/* Decrement FPROM addr. Counter */#define LD_START		BIT_0S	/* Start loading FPROM *//* *	Timer Section *//*	B2_TI_CRTL	 8 bit	Timer control *//*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */								/* Bit 7.. 3:	reserved */#define TIM_START		BIT_2S	/* Start Timer */#define TIM_STOP		BIT_1S	/* Stop  Timer */#define TIM_CLR_IRQ		BIT_0S	/* Clear Timer IRQ (!IRQM) *//*	B2_TI_TEST	 8 Bit	Timer Test *//*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test *//*	B28_DPT_TST	 8 bit	Descriptor Poll Timer Test Reg */								/* Bit 7.. 3:	reserved */#define TIM_T_ON		BIT_2S	/* Test mode on */#define TIM_T_OFF		BIT_1S	/* Test mode off */#define TIM_T_STEP		BIT_0S	/* Test step *//*	B28_DPT_INI	32 bit	Descriptor Poll Timer Init Val *//*	B28_DPT_VAL	32 bit	Descriptor Poll Timer Curr Val */								/* Bit 31..24:	reserved */#define DPT_MSK		0x00ffffffL	/* Bit 23.. 0:	Desc Poll Timer Bits *//*	B28_DPT_CTRL	 8 bit	Descriptor Poll Timer Ctrl Reg */								/* Bit  7.. 2:	reserved */#define DPT_START		BIT_1S	/* Start Descriptor Poll Timer */#define DPT_STOP		BIT_0S	/* Stop  Descriptor Poll Timer *//*	B2_E_3			 8 bit 	lower 4 bits used for HW self test result */#define B2_E3_RES_MASK	0x0f/*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */#define TST_FRC_DPERR_MR	BIT_7S	/* force DATAPERR on MST RD */#define TST_FRC_DPERR_MW	BIT_6S	/* force DATAPERR on MST WR */#define TST_FRC_DPERR_TR	BIT_5S	/* force DATAPERR on TRG RD */#define TST_FRC_DPERR_TW	BIT_4S	/* force DATAPERR on TRG WR */#define TST_FRC_APERR_M		BIT_3S	/* force ADDRPERR on MST */#define TST_FRC_APERR_T		BIT_2S	/* force ADDRPERR on TRG */#define TST_CFG_WRITE_ON	BIT_1S	/* Enable  Config Reg WR */#define TST_CFG_WRITE_OFF	BIT_0S	/* Disable Config Reg WR *//*	B2_TST_CTRL2	 8 bit	Test Control Register 2 */									/* Bit 7.. 4:	reserved */			/* force the following error on the next master read/write	*/#define TST_FRC_DPERR_MR64	BIT_3S	/* DataPERR RD 64	*/#define TST_FRC_DPERR_MW64	BIT_2S	/* DataPERR WR 64	*/#define TST_FRC_APERR_1M64	BIT_1S	/* AddrPERR on 1. phase */#define TST_FRC_APERR_2M64	BIT_0S	/* AddrPERR on 2. phase *//*	B2_GP_IO	32 bit	General Purpose I/O Register */							/* Bit 31..26:	reserved */#define GP_DIR_9	BIT_25	/* IO_9 direct, 0=I/1=O */#define GP_DIR_8	BIT_24	/* IO_8 direct, 0=I/1=O */#define GP_DIR_7	BIT_23	/* IO_7 direct, 0=I/1=O */#define GP_DIR_6	BIT_22	/* IO_6 direct, 0=I/1=O */#define GP_DIR_5	BIT_21	/* IO_5 direct, 0=I/1=O */#define GP_DIR_4	BIT_20	/* IO_4 direct, 0=I/1=O */#define GP_DIR_3	BIT_19	/* IO_3 direct, 0=I/1=O */#define GP_DIR_2	BIT_18	/* IO_2 direct, 0=I/1=O */#define GP_DIR_1	BIT_17	/* IO_1 direct, 0=I/1=O */#define GP_DIR_0	BIT_16	/* IO_0 direct, 0=I/1=O */						/* Bit 15..10:	reserved */#define GP_IO_9		BIT_9	/* IO_9 pin */#define GP_IO_8		BIT_8	/* IO_8 pin */#define GP_IO_7		BIT_7	/* IO_7 pin */#define GP_IO_6		BIT_6	/* IO_6 pin */#define GP_IO_5		BIT_5	/* IO_5 pin */#define GP_IO_4		BIT_4	/* IO_4 pin */#define GP_IO_3		BIT_3	/* IO_3 pin */#define GP_IO_2		BIT_2	/* IO_2 pin */#define GP_IO_1		BIT_1	/* IO_1 pin */#define GP_IO_0		BIT_0	/* IO_0 pin *//*	B2_I2C_CTRL	32 bit	I2C HW Control Register */#define I2C_FLAG		BIT_31		/* Start read/write if WR */#define I2C_ADDR		(0x7fffL<<16)	/* Bit 30..16:	Addr to be RD/WR */#define I2C_DEV_SEL		(0x7fL<<9)		/* Bit 15.. 9:	I2C Device Select */								/* Bit	8.. 5:	reserved	*/#define I2C_BURST_LEN	BIT_4		/* Burst Len, 1/4 bytes */#define I2C_DEV_SIZE	(7L<<1)		/* Bit	3.. 1:	I2C Device Size	*/#define I2C_025K_DEV	(0L<<1)		/*		0: 256 Bytes or smal. */#define I2C_05K_DEV		(1L<<1)		/* 		1: 512	Bytes	*/#define I2C_1K_DEV		(2L<<1)		/*		2: 1024 Bytes	*/#define I2C_2K_DEV		(3L<<1)		/*		3: 2048	Bytes	*/#define I2C_4K_DEV		(4L<<1)		/*		4: 4096 Bytes	*/#define I2C_8K_DEV		(5L<<1)		/*		5: 8192 Bytes	*/#define I2C_16K_DEV		(6L<<1)		/*		6: 16384 Bytes	*/#define I2C_32K_DEV		(7L<<1)		/*		7: 32768 Bytes	*/#define I2C_STOP		BIT_0		/* Interrupt I2C transfer *//*	B2_I2C_IRQ	32 bit	I2C HW IRQ Register */								/* Bit 31.. 1	reserved */#define I2C_CLR_IRQ		BIT_0	/* Clear I2C IRQ *//*	B2_I2C_SW	32 bit (8 bit access)	I2C HW SW Port Register */								/* Bit  7.. 3:	reserved */#define I2C_DATA_DIR	BIT_2S		/* direction of I2C_DATA */#define I2C_DATA		BIT_1S		/* I2C Data Port	*/#define I2C_CLK			BIT_0S		/* I2C Clock Port	*//* * I2C Address */#define I2C_SENS_ADDR	LM80_ADDR	/* I2C Sensor Address, (Volt and Temp)*//*	B2_BSC_CTRL	 8 bit	Blink Source Counter Control */							/* Bit  7.. 2:	reserved */#define BSC_START	BIT_1S		/* Start Blink Source Counter */#define BSC_STOP	BIT_0S		/* Stop  Blink Source Counter *//*	B2_BSC_STAT	 8 bit	Blink Source Counter Status */							/* Bit  7.. 1:	reserved */