if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {		return(1);	}	/* Return to D0 state. */	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);	/* Check for D0 state. */	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);	if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {		return(1);	}	/* Check PCI Config Registers. */	SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);	SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);	SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);	SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);	SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);	if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||		Lat != 0) {		return(1);	}	/* Restore PCI Config Space. */	for (i = 0; i < PCI_CFG_SIZE; i++) {		SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);	}	return(0);}	/* SkGePciReset */#endif /* SK_PCI_RESET *//****************************************************************************** * *	SkGeInit1() - Level 1 Initialization * * Description: *	o Do a software reset. *	o Clear all reset bits. *	o Verify that the detected hardware is present. *	  Return an error if not. *	o Get the hardware configuration *		+ Read the number of MACs/Ports. *		+ Read the RAM size. *		+ Read the PCI Revision Id. *		+ Find out the adapters host clock speed *		+ Read and check the PHY type * * Returns: *	0:	success *	5:	Unexpected PHY type detected *	6:	HW self test failed */static int SkGeInit1(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC)		/* IO context */{	SK_U8	Byte;	SK_U16	Word;	SK_U16	CtrlStat;	SK_U32	FlashAddr;	int	RetVal;	int	i;	RetVal = 0;	/* save CLK_RUN bits (YUKON-Lite) */	SK_IN16(IoC, B0_CTST, &CtrlStat);#ifdef SK_PCI_RESET	(void)SkGePciReset(pAC, IoC);#endif /* SK_PCI_RESET */	/* do the SW-reset */	SK_OUT8(IoC, B0_CTST, CS_RST_SET);	/* release the SW-reset */	SK_OUT8(IoC, B0_CTST, CS_RST_CLR);	/* reset all error bits in the PCI STATUS register */	/*	 * Note: PCI Cfg cycles cannot be used, because they are not	 *		 available on some platforms after 'boot time'.	 */	SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);	SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);	SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);	SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);	/* release Master Reset */	SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);#ifdef CLK_RUN	CtrlStat |= CS_CLK_RUN_ENA;#endif /* CLK_RUN */	/* restore CLK_RUN bits */	SK_OUT16(IoC, B0_CTST, CtrlStat &		(CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA));	/* read Chip Identification Number */	SK_IN8(IoC, B2_CHIP_ID, &Byte);	pAC->GIni.GIChipId = Byte;	/* read number of MACs */	SK_IN8(IoC, B2_MAC_CFG, &Byte);	pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;	/* get Chip Revision Number */	pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);	/* get diff. PCI parameters */	SK_IN16(IoC, B0_CTST, &CtrlStat);	/* read the adapters RAM size */	SK_IN8(IoC, B2_E_0, &Byte);	if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {		pAC->GIni.GIGenesis = SK_TRUE;		if (Byte == 3) {			/* special case: 4 x 64k x 36, offset = 0x80000 */			pAC->GIni.GIRamSize = 1024;			pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;		}		else {			pAC->GIni.GIRamSize = (int)Byte * 512;			pAC->GIni.GIRamOffs = 0;		}		/* all GE adapters work with 53.125 MHz host clock */		pAC->GIni.GIHstClkFact = SK_FACT_53;		/* set Descr. Poll Timer Init Value to 250 ms */		pAC->GIni.GIPollTimerVal =			SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;	}	else {		pAC->GIni.GIGenesis = SK_FALSE;#ifndef VCPU		pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4;#else		pAC->GIni.GIRamSize = 128;#endif		pAC->GIni.GIRamOffs = 0;		/* WA for chip Rev. A */		pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;		/* get PM Capabilities of PCI config space */		SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);		/* check if VAUX is available */		if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&			/* check also if PME from D3cold is set */			((Word & PCI_PME_D3C_SUP) != 0)) {			/* set entry in GE init struct */			pAC->GIni.GIVauxAvail = SK_TRUE;		}		/* save Flash-Address Register */		SK_IN32(IoC, B2_FAR, &FlashAddr);		/* test Flash-Address Register */		SK_OUT8(IoC, B2_FAR + 3, 0xff);		SK_IN8(IoC, B2_FAR + 3, &Byte);		pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0);		/* restore Flash-Address Register */		SK_OUT32(IoC, B2_FAR, FlashAddr);		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {			/* set GMAC Link Control reset */			SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);			/* clear GMAC Link Control reset */			SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);		}		/* all YU chips work with 78.125 MHz host clock */		pAC->GIni.GIHstClkFact = SK_FACT_78;		pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;	/* 215 ms */	}	/* check if 64-bit PCI Slot is present */	pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);	/* check if 66 MHz PCI Clock is active */	pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);	/* read PCI HW Revision Id. */	SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);	pAC->GIni.GIPciHwRev = Byte;	/* read the PMD type */	SK_IN8(IoC, B2_PMD_TYP, &Byte);	pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');	/* read the PHY type */	SK_IN8(IoC, B2_E_1, &Byte);	Byte &= 0x0f;	/* the PHY type is stored in the lower nibble */	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {		if (pAC->GIni.GIGenesis) {			switch (Byte) {			case SK_PHY_XMAC:				pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;				break;			case SK_PHY_BCOM:				pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;				pAC->GIni.GP[i].PMSCap =					SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE;				break;#ifdef OTHER_PHY			case SK_PHY_LONE:				pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;				break;			case SK_PHY_NAT:				pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;				break;#endif /* OTHER_PHY */			default:				/* ERROR: unexpected PHY type detected */				RetVal = 5;				break;			}		}		else {			if (Byte == 0) {				/* if this field is not initialized */				Byte = SK_PHY_MARV_COPPER;				pAC->GIni.GICopperType = SK_TRUE;			}			pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;			if (pAC->GIni.GICopperType) {				pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO |					SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |					SK_LSPEED_CAP_1000MBPS;				pAC->GIni.GP[i].PLinkSpeed = SK_LSPEED_AUTO;				pAC->GIni.GP[i].PMSCap =					SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE;			}			else {				Byte = SK_PHY_MARV_FIBER;			}		}		pAC->GIni.GP[i].PhyType = Byte;		SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,			("PHY type: %d  PHY addr: %04x\n", Byte,			pAC->GIni.GP[i].PhyAddr));	}	/* get Mac Type & set function pointers dependent on */	if (pAC->GIni.GIGenesis) {		pAC->GIni.GIMacType = SK_MAC_XMAC;		pAC->GIni.GIFunc.pFnMacUpdateStats	= SkXmUpdateStats;		pAC->GIni.GIFunc.pFnMacStatistic	= SkXmMacStatistic;		pAC->GIni.GIFunc.pFnMacResetCounter	= SkXmResetCounter;		pAC->GIni.GIFunc.pFnMacOverflow		= SkXmOverflowStatus;	}	else {		pAC->GIni.GIMacType = SK_MAC_GMAC;		pAC->GIni.GIFunc.pFnMacUpdateStats	= SkGmUpdateStats;		pAC->GIni.GIFunc.pFnMacStatistic	= SkGmMacStatistic;		pAC->GIni.GIFunc.pFnMacResetCounter	= SkGmResetCounter;		pAC->GIni.GIFunc.pFnMacOverflow		= SkGmOverflowStatus;#ifdef SPECIAL_HANDLING		if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {			/* check HW self test result */			SK_IN8(IoC, B2_E_3, &Byte);			if ((Byte & B2_E3_RES_MASK) != 0) {				RetVal = 6;			}		}#endif	}	return(RetVal);}	/* SkGeInit1 *//****************************************************************************** * *	SkGeInit2() - Level 2 Initialization * * Description: *	- start the Blink Source Counter *	- start the Descriptor Poll Timer *	- configure the MAC-Arbiter *	- configure the Packet-Arbiter *	- enable the Tx Arbiters *	- enable the RAM Interface Arbiter * * Returns: *	nothing */static void SkGeInit2(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC)		/* IO context */{	SK_U32	DWord;	int		i;	/* start the Descriptor Poll Timer */	if (pAC->GIni.GIPollTimerVal != 0) {		if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {			pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);		}		SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);		SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);	}	if (pAC->GIni.GIGenesis) {		/* start the Blink Source Counter */		DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;		SK_OUT32(IoC, B2_BSC_INI, DWord);		SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);		/*		 * Configure the MAC Arbiter and the Packet Arbiter.		 * They will be started once and never be stopped.		 */		SkGeInitMacArb(pAC, IoC);		SkGeInitPktArb(pAC, IoC);	}	else {		/* start Time Stamp Timer */		SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);	}	/* enable the Tx Arbiters */	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {		SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);	}	/* enable the RAM Interface Arbiter */	SkGeInitRamIface(pAC, IoC);}	/* SkGeInit2 *//****************************************************************************** * *	SkGeInit() - Initialize the GE Adapter with the specified level. * * Description: *	Level	0:	Initialize the Module structures. *	Level	1:	Generic Hardware Initialization. The IOP/MemBase pointer has *				to be set before calling this level. * *			o Do a software reset. *			o Clear all reset bits. *			o Verify that the detected hardware is present. *			  Return an error if not. *			o Get the hardware configuration *				+ Set GIMacsFound with the number of MACs. *				+ Store the RAM size in GIRamSize. *				+ Save the PCI Revision ID in GIPciHwRev. *			o return an error *				if Number of MACs > SK_MAX_MACS * *			After returning from Level 0 the adapter *			may be accessed with IO operations. * *	Level	2:	start the Blink Source Counter * * Returns: *	0:	success *	1:	Number of MACs exceeds SK_MAX_MACS	(after level 1) *	2:	Adapter not present or not accessible *	3:	Illegal initialization level *	4:	Initialization Level 1 Call missing *	5:	Unexpected PHY type detected *	6:	HW self test failed */int	SkGeInit(SK_AC	*pAC,		/* adapter context */SK_IOC	IoC,		/* IO context */int		Level)		/* initialization level */{	int		RetVal;		/* return value */	SK_U32	DWord;	RetVal = 0;	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,		("SkGeInit(Level %d)\n", Level));	switch (Level) {	case SK_INIT_DATA:		/* Initialization Level 0 */		SkGeInit0(pAC, IoC);		pAC->GIni.GILevel = SK_INIT_DATA;		break;	case SK_INIT_IO:		/* Initialization Level 1 */		RetVal = SkGeInit1(pAC, IoC);		if (RetVal != 0) {			break;		}		/* check if the adapter seems to be accessible */		SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);		SK_IN32(IoC, B2_IRQM_INI, &DWord);		SK_OUT32(IoC, B2_IRQM_INI, 0L);		if (DWord != 0x11335577L) {			RetVal = 2;			break;		}		/* check if the number of GIMacsFound matches SK_MAX_MACS */		if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {			RetVal = 1;			break;		}		/* Level 1 successfully passed */		pAC->GIni.GILevel = SK_INIT_IO;		break;	case SK_INIT_RUN:		/* Initialization Level 2 */		if (pAC->GIni.GILevel != SK_INIT_IO) {#ifndef SK_DIAG			SK_E