?? at91sam9263.h
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#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
#define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface 1
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EBI1 {
AT91_REG EBI1_DUMMY; // Dummy register - Do not use
} AT91S_EBI1, *AT91PS_EBI1;
#else
#define EBI1_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI1_DUMMY) Dummy register - Do not use
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_MATRIX {
AT91_REG MATRIX_MCFG0; // Master Configuration Register 0
AT91_REG MATRIX_MCFG1; // Master Configuration Register 1
AT91_REG MATRIX_MCFG2; // Master Configuration Register 2
AT91_REG MATRIX_MCFG3; // Master Configuration Register 3
AT91_REG MATRIX_MCFG4; // Master Configuration Register 4
AT91_REG MATRIX_MCFG5; // Master Configuration Register 5
AT91_REG MATRIX_MCFG6; // Master Configuration Register 6
AT91_REG MATRIX_MCFG7; // Master Configuration Register 7
AT91_REG MATRIX_MCFG8; // Master Configuration Register 8
AT91_REG Reserved0[7]; //
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
AT91_REG MATRIX_SCFG5; // Slave Configuration Register 5
AT91_REG MATRIX_SCFG6; // Slave Configuration Register 6
AT91_REG MATRIX_SCFG7; // Slave Configuration Register 7
AT91_REG Reserved1[8]; //
AT91_REG MATRIX_PRAS0; // PRAS0
AT91_REG MATRIX_PRBS0; // PRBS0
AT91_REG MATRIX_PRAS1; // PRAS1
AT91_REG MATRIX_PRBS1; // PRBS1
AT91_REG MATRIX_PRAS2; // PRAS2
AT91_REG MATRIX_PRBS2; // PRBS2
AT91_REG MATRIX_PRAS3; // PRAS3
AT91_REG MATRIX_PRBS3; // PRBS3
AT91_REG MATRIX_PRAS4; // PRAS4
AT91_REG MATRIX_PRBS4; // PRBS4
AT91_REG MATRIX_PRAS5; // PRAS5
AT91_REG MATRIX_PRBS5; // PRBS5
AT91_REG MATRIX_PRAS6; // PRAS6
AT91_REG MATRIX_PRBS6; // PRBS6
AT91_REG MATRIX_PRAS7; // PRAS7
AT91_REG MATRIX_PRBS7; // PRBS7
AT91_REG Reserved2[16]; //
AT91_REG MATRIX_MRCR; // Master Remp Control Register
} AT91S_MATRIX, *AT91PS_MATRIX;
#else
#define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0
#define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1
#define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2
#define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3
#define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4
#define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5
#define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6
#define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7
#define MATRIX_MCFG8 (AT91_CAST(AT91_REG *) 0x00000020) // (MATRIX_MCFG8) Master Configuration Register 8
#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0
#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1
#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2
#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3
#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4
#define MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0x00000054) // (MATRIX_SCFG5) Slave Configuration Register 5
#define MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0x00000058) // (MATRIX_SCFG6) Slave Configuration Register 6
#define MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0x0000005C) // (MATRIX_SCFG7) Slave Configuration Register 7
#define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0
#define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0
#define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1
#define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1
#define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2
#define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2
#define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3
#define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3
#define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4
#define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4
#define MATRIX_PRAS5 (AT91_CAST(AT91_REG *) 0x000000A8) // (MATRIX_PRAS5) PRAS5
#define MATRIX_PRBS5 (AT91_CAST(AT91_REG *) 0x000000AC) // (MATRIX_PRBS5) PRBS5
#define MATRIX_PRAS6 (AT91_CAST(AT91_REG *) 0x000000B0) // (MATRIX_PRAS6) PRAS6
#define MATRIX_PRBS6 (AT91_CAST(AT91_REG *) 0x000000B4) // (MATRIX_PRBS6) PRBS6
#define MATRIX_PRAS7 (AT91_CAST(AT91_REG *) 0x000000B8) // (MATRIX_PRAS7) PRAS7
#define MATRIX_PRBS7 (AT91_CAST(AT91_REG *) 0x000000BC) // (MATRIX_PRBS7) PRBS7
#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remap Control Register
#endif
// -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom --------
#define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type
// -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm --------
// -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm --------
// -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs --------
// -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 --------
// -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 --------
// -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge --------
// -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps --------
// -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register gps --------
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
#define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_USB (0x8 << 18) // (MATRIX) USB Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ISI (0x5 << 18) // (MATRIX) ISI Master is Defau?? 快捷鍵說明
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