/************************************************************************
 *
 *  mips.h
 *
 *  MIPS processor definitions
 *
 *  The basic CPU definitions are found in the file ArchDefs.h, which
 *  is included by mips.h.
 *
 *  mips.h implements aliases for some of the definitions in ArchDefs.h
 *  and adds various definitions.
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved.
 *
 * Unpublished rights reserved under the Copyright Laws of the United States of
 * America.
 *
 * This document contains information that is proprietary to MIPS Technologies,
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information
 * (in whole or in part) which is not expressly permitted in writing by MIPS
 * Technologies or a contractually-authorized third party is strictly
 * prohibited. At a minimum, this information is protected under unfair
 * competition laws and the expression of the information contained herein is
 * protected under federal copyright laws. Violations thereof may result in
 * criminal penalties and fines.
 * MIPS Technologies or any contractually-authorized third party reserves the
 * right to change the information contained in this document to improve
 * function, design or otherwise. MIPS Technologies does not assume any
 * liability arising out of the application or use of this information. Any
 * license under patent rights or any other intellectual property rights owned
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies
 * or any contractually-authorized third party in a separate license agreement
 * between the parties.
 * The information contained in this document constitutes one or more of the
 * following: commercial computer software, commercial computer software
 * documentation or other commercial items. If the user of this information, or
 * any related documentation of any kind, including related technical data or
 * manuals, is an agency, department, or other entity of the United States
 * government ("Government"), the use, duplication, reproduction, release,
 * modification, disclosure, or transfer of this information, or any related
 * documentation of any kind, is restricted in accordance with Federal
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of
 * this information by the Government is further restricted in accordance with
 * the terms of the license agreement(s) and/or applicable contract terms and
 * conditions covering this information from MIPS Technologies or any
 * contractually-authorized third party.
 *
 ************************************************************************/

#ifndef MIPS_H
#define MIPS_H

/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <ArchDefs.h>

/************************************************************************
 *  Definitions
*************************************************************************/

/* CPU registers */
#define SYS_CPUREG_ZERO	0
#define SYS_CPUREG_AT	1
#define SYS_CPUREG_V0	2
#define SYS_CPUREG_V1	3
#define SYS_CPUREG_A0	4
#define SYS_CPUREG_A1	5
#define SYS_CPUREG_A2	6
#define SYS_CPUREG_A3	7
#define SYS_CPUREG_T0	8
#define SYS_CPUREG_T1	9
#define SYS_CPUREG_T2	10
#define SYS_CPUREG_T3	11
#define SYS_CPUREG_T4	12
#define SYS_CPUREG_T5	13
#define SYS_CPUREG_T6	14
#define SYS_CPUREG_T7	15
#define SYS_CPUREG_S0	16
#define SYS_CPUREG_S1	17
#define SYS_CPUREG_S2	18
#define SYS_CPUREG_S3	19
#define SYS_CPUREG_S4	20
#define SYS_CPUREG_S5	21
#define SYS_CPUREG_S6	22
#define SYS_CPUREG_S7	23
#define SYS_CPUREG_T8	24
#define SYS_CPUREG_T9	25
#define SYS_CPUREG_K0	26
#define SYS_CPUREG_K1	27
#define SYS_CPUREG_GP	28
#define SYS_CPUREG_SP	29
#define SYS_CPUREG_S8	30
#define SYS_CPUREG_FP	SYS_CPUREG_S8
#define SYS_CPUREG_RA	31


/* CPU register fp ($30) has an alias s8 */
#define s8		fp


/* Aliases for System Control Coprocessor (CP0) registers */
#define C0_INDEX	C0_Index
#define C0_RANDOM	C0_Random
#define C0_ENTRYLO0	C0_EntryLo0
#define C0_ENTRYLO1	C0_EntryLo1
#define C0_CONTEXT	C0_Context
#define C0_PAGEMASK	C0_PageMask
#define C0_WIRED	C0_Wired
#define C0_BADVADDR	C0_BadVAddr
#define C0_COUNT 	C0_Count
#define C0_ENTRYHI	C0_EntryHi
#define C0_COMPARE	C0_Compare
#define C0_STATUS	C0_Status
#define C0_CAUSE	C0_Cause

#ifdef C0_PRID	/* ArchDefs has an obsolete def. of C0_PRID */
#undef C0_PRID
#endif
#define C0_PRID		C0_PRId

#define C0_CONFIG	C0_Config
#define C0_CONFIG1	C0_Config1
#define C0_LLADDR	C0_LLAddr
#define C0_WATCHLO	C0_WatchLo
#define C0_WATCHHI	C0_WatchHi
#define C0_DEBUG        C0_Debug
#define C0_PERFCNT      C0_PerfCnt
#define C0_ERRCTL	C0_ErrCtl
#define C0_CACHEERR	C0_CacheErr
#define C0_TAGLO	C0_TagLo
#define C0_DATALO	C0_DataLo
#define C0_TAGHI	C0_TagHi
#define C0_DATAHI	C0_DataHi
#define C0_ERROREPC	C0_ErrorEPC
#if 0
#define C0_DESAVE	C0_DESAVE
#define C0_EPC		C0_EPC
#define C0_DEPC         C0_DEPC
#endif

/* System Control Coprocessor (CP0) registers select fields */
#define C0_INDEX_SEL	0		/* TLB Index */
#define C0_RANDOM_SEL	0		/* TLB Random */
#define C0_TLBLO0_SEL	0		/* TLB EntryLo0 */
#define C0_TLBLO1_SEL	0		/* TLB EntryLo1 */
#define C0_CONTEXT_SEL	0		/* Context */
#define C0_PAGEMASK_SEL	0		/* TLB PageMask */
#define C0_WIRED_SEL	0		/* TLB Wired */
#define C0_BADVADDR_SEL	0		/* Bad Virtual Address */
#define C0_COUNT_SEL	0		/* Count */
#define C0_ENTRYHI_SEL	0		/* TLB EntryHi */
#define C0_COMPARE_SEL	0		/* Compare */
#define C0_STATUS_SEL	0		/* Processor Status */
#define C0_CAUSE_SEL	0		/* Exception Cause */
#define C0_EPC_SEL	0		/* Exception PC */
#define C0_PRID_SEL	0		/* Processor Revision Indentifier */
#define C0_CONFIG_SEL	0		/* Config */
#define C0_CONFIG1_SEL	1		/* Config1 */
#define C0_LLADDR_SEL	0		/* LLAddr */
#define C0_WATCHLO_SEL	0		/* WatchpointLo */
#define C0_WATCHHI_SEL	0		/* WatchpointHi */
#define C0_DEBUG_SEL    0		/* EJTAG Debug Register */
#define C0_DEPC_SEL     0		/* Program counter at last EJTAG debug exception */
#define C0_PERFCNT_SEL  0		/* Performance counter interface */
#define C0_ERRCTL_SEL	0		/* ECC */
#define C0_CACHEERR_SEL	0		/* CacheErr */
#define C0_TAGLO_SEL	0		/* TagLo */
#define C0_DATALO_SEL	1		/* DataLo */
#define C0_TAGHI_SEL	0		/* TagHi */
#define C0_DATAHI_SEL	1		/* DataHi */
#define C0_ERROREPC_SEL	0		/* ErrorEPC */
#define C0_DESAVE_SEL	0		/* EJTAG dbg exc. save register */


/* C0_CONFIG register encoding */

#define C0_CONFIG_M_SHF			S_ConfigMore
#define C0_CONFIG_M_MSK     		M_ConfigMore
#define C0_CONFIG_M_BIT			C0_CONFIG_M_MSK

#define C0_CONFIG_BE_SHF		S_ConfigBE
#define C0_CONFIG_BE_MSK    		M_ConfigBE
#define C0_CONFIG_BE_BIT		C0_CONFIG_BE_MSK

#define C0_CONFIG_AT_SHF		S_ConfigAT
#define C0_CONFIG_AT_MSK		M_ConfigAT
#define C0_CONFIG_AT_MIPS32		K_ConfigAT_MIPS32
#define C0_CONFIG_AT_MIPS64_32ADDR	K_ConfigAT_MIPS64S
#define C0_CONFIG_AT_MIPS64		K_ConfigAT_MIPS64

#define C0_CONFIG_AR_SHF		S_ConfigAR
#define C0_CONFIG_AR_MSK		M_ConfigAR

#define C0_CONFIG_MT_SHF		S_ConfigMT
#define C0_CONFIG_MT_MSK		M_ConfigMT
#define C0_CONFIG_MT_NONE		K_ConfigMT_NoMMU
#define C0_CONFIG_MT_TLB		K_ConfigMT_TLBMMU
#define C0_CONFIG_MT_BAT		K_ConfigMT_BATMMU
#define C0_CONFIG_MT_NON_STD		K_ConfigMT_FMMMU

#define C0_CONFIG_K0_SHF		S_ConfigK0
#define C0_CONFIG_K0_MSK		M_ConfigK0
#define C0_CONFIG_K0_WTHRU_NOALLOC	K_CacheAttrCWTnWA
#define C0_CONFIG_K0_WTHRU_ALLOC	K_CacheAttrCWTWA
#define C0_CONFIG_K0_UNCACHED		K_CacheAttrU
#define C0_CONFIG_K0_NONCOHERENT	K_CacheAttrCN
#define C0_CONFIG_K0_COHERENTXCL	K_CacheAttrCCE
#define C0_CONFIG_K0_COHERENTXCLW	K_CacheAttrCCS
#define C0_CONFIG_K0_COHERENTUPD	K_CacheAttrCCU
#define C0_CONFIG_K0_UNCACHED_ACCEL	K_CacheAttrUA


/*  WC field.
 *
 *  This feature is present specifically to support configuration
 *  testing of the core in a lead vehicle, and is not supported
 *  in any other environment.  Attempting to use this feature
 *  outside of the scope of a lead vehicle is a violation of the
 *  MIPS Architecture, and may cause unpredictable operation of
 *  the processor.
 */
#define C0_CONFIG_WC_SHF		19
#define C0_CONFIG_WC_MSK    		(MSK(1) << C0_CONFIG_WC_SHF)
#define C0_CONFIG_WC_BIT		C0_CONFIG_WC_MSK


/* C0_CONFIG1 register encoding */

#define C0_CONFIG1_MMUSIZE_SHF		S_Config1MMUSize
#define C0_CONFIG1_MMUSIZE_MSK		M_Config1MMUSize

#define C0_CONFIG1_IS_SHF		S_Config1IS
#define C0_CONFIG1_IS_MSK		M_Config1IS

#define C0_CONFIG1_IL_SHF		S_Config1IL
#define C0_CONFIG1_IL_MSK		M_Config1IL

#define C0_CONFIG1_IA_SHF		S_Config1IA
#define C0_CONFIG1_IA_MSK		M_Config1IA

#define C0_CONFIG1_DS_SHF		S_Config1DS
#define C0_CONFIG1_DS_MSK		M_Config1DS

#define C0_CONFIG1_DL_SHF		S_Config1DL
#define C0_CONFIG1_DL_MSK		M_Config1DL

#define C0_CONFIG1_DA_SHF		S_Config1DA
#define C0_CONFIG1_DA_MSK		M_Config1DA

#define C0_CONFIG1_WR_SHF		S_Config1WR
#define C0_CONFIG1_WR_MSK		M_Config1WR
#define C0_CONFIG1_WR_BIT		C0_CONFIG1_WR_MSK

#define C0_CONFIG1_CA_SHF		S_Config1CA
#define C0_CONFIG1_CA_MSK		M_Config1CA
#define C0_CONFIG1_CA_BIT		C0_CONFIG1_CA_MSK

#define C0_CONFIG1_FP_SHF		S_Config1FP
#define C0_CONFIG1_FP_MSK		M_Config1FP
#define C0_CONFIG1_FP_BIT		C0_CONFIG1_FP_MSK


/* C0_STATUS register encoding */

#define C0_STATUS_CU3_SHF		S_StatusCU3
#define C0_STATUS_CU3_MSK		M_StatusCU3
#define C0_STATUS_CU3_BIT		C0_STATUS_CU3_MSK

#define C0_STATUS_CU2_SHF		S_StatusCU2
#define C0_STATUS_CU2_MSK		M_StatusCU2
#define C0_STATUS_CU2_BIT		C0_STATUS_CU2_MSK

#define C0_STATUS_CU1_SHF		S_StatusCU1
#define C0_STATUS_CU1_MSK		M_StatusCU1
#define C0_STATUS_CU1_BIT		C0_STATUS_CU1_MSK

#define C0_STATUS_CU0_SHF		S_StatusCU1
#define C0_STATUS_CU0_MSK		M_StatusCU1
#define C0_STATUS_CU0_BIT		C0_STATUS_CU0_MSK

#define C0_STATUS_RP_SHF		S_StatusRP
#define C0_STATUS_RP_MSK		M_StatusRP
#define C0_STATUS_RP_BIT		C0_STATUS_RP_MSK

#define C0_STATUS_RE_SHF		S_StatusRE
#define C0_STATUS_RE_MSK		M_StatusRE
#define C0_STATUS_RE_BIT		C0_STATUS_RE_MSK

#define C0_STATUS_BEV_SHF		S_StatusBEV
#define C0_STATUS_BEV_MSK		M_StatusBEV
#define C0_STATUS_BEV_BIT		C0_STATUS_BEV_MSK

#define C0_STATUS_TS_SHF		S_StatusTS
#define C0_STATUS_TS_MSK		M_StatusTS
#define C0_STATUS_TS_BIT		C0_STATUS_TS_MSK

#define C0_STATUS_SR_SHF		S_StatusSR
#define C0_STATUS_SR_MSK		M_StatusSR
#define C0_STATUS_SR_BIT		C0_STATUS_SR_MSK

#define C0_STATUS_NMI_SHF		S_StatusNMI
#define C0_STATUS_NMI_MSK		M_StatusNMI
#define C0_STATUS_NMI_BIT		C0_STATUS_NMI_MSK

#define C0_STATUS_IM_SHF		S_StatusIM
#define C0_STATUS_IM_MSK		M_StatusIM
/*  Note that the the definitions below indicate the interrupt number
 *  rather than the mask.
 *  (0..1 for SW interrupts and 2...7 for HW interrupts)
 */
#define C0_STATUS_IM_SW0		(S_StatusIM0 - S_StatusIM)
#define C0_STATUS_IM_SW1		(S_StatusIM1 - S_StatusIM)
#define C0_STATUS_IM_HW0		(S_StatusIM2 - S_StatusIM)
#define C0_STATUS_IM_HW1		(S_StatusIM3 - S_StatusIM)
#define C0_STATUS_IM_HW2		(S_StatusIM4 - S_StatusIM)
#define C0_STATUS_IM_HW3		(S_StatusIM5 - S_StatusIM)
#define C0_STATUS_IM_HW4		(S_StatusIM6 - S_StatusIM)
#define C0_STATUS_IM_HW5		(S_StatusIM7 - S_StatusIM)