/////////////////////////////////////////////////////////////////////////                                                             ////////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////////                                                             ////////                                                             ////////  Author: Richard Herveille                                  ////////          richard@asics.ws                                   ////////          www.asics.ws                                       ////////                                                             ////////  Downloaded from: http://www.opencores.org/projects/i2c/    ////////                                                             /////////////////////////////////////////////////////////////////////////////                                                             //////// Copyright (C) 2001 Richard Herveille                        ////////                    richard@asics.ws                         ////////                                                             //////// This source file may be used and distributed without        //////// restriction provided that this copyright statement is not   //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer.////////                                                             ////////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     //////// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   //////// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   //////// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      //////// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         //////// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    //////// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   //////// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        //////// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  //////// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  //////// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  //////// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         //////// POSSIBILITY OF SUCH DAMAGE.                                 ////////                                                             ///////////////////////////////////////////////////////////////////////////  CVS Log////  $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $////  $Date: 2006/09/04 09:08:13 $//  $Revision: 1.12 $//  $Author: rherveille $//  $Locker:  $//  $State: Exp $//// Change History://               $Log: i2c_master_bit_ctrl.v,v $//               Revision 1.12  2006/09/04 09:08:13  rherveille//               fixed short scl high pulse after clock stretch//               fixed slave model not returning correct '(n)ack' signal////               Revision 1.11  2004/05/07 11:02:26  rherveille//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.////               Revision 1.10  2003/08/09 07:01:33  rherveille//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.//               Fixed a potential bug in the byte controller's host-acknowledge generation.////               Revision 1.9  2003/03/10 14:26:37  rherveille//               Fixed cmd_ack generation item (no bug).////               Revision 1.8  2003/02/05 00:06:10  rherveille//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.////               Revision 1.7  2002/12/26 16:05:12  rherveille//               Small code simplifications////               Revision 1.6  2002/12/26 15:02:32  rherveille//               Core is now a Multimaster I2C controller////               Revision 1.5  2002/11/30 22:24:40  rherveille//               Cleaned up code////               Revision 1.4  2002/10/30 18:10:07  rherveille//               Fixed some reported minor start/stop generation timing issuess.////               Revision 1.3  2002/06/15 07:37:03  rherveille//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.////               Revision 1.2  2001/11/05 11:59:25  rherveille//               Fixed wb_ack_o generation bug.//               Fixed bug in the byte_controller statemachine.//               Added headers./////////////////////////////////////////// Bit controller section///////////////////////////////////////// Translate simple commands into SCL/SDA transitions// Each command has 5 states, A/B/C/D/idle//// start:	SCL	~~~~~~~~~~\____//	SDA	~~~~~~~~\______//		 x | A | B | C | D | i//// repstart	SCL	____/~~~~\___//	SDA	__/~~~\______//		 x | A | B | C | D | i//// stop	SCL	____/~~~~~~~~//	SDA	==\____/~~~~~//		 x | A | B | C | D | i////- write	SCL	____/~~~~\____//	SDA	==X=========X=//		 x | A | B | C | D | i////- read	SCL	____/~~~~\____//	SDA	XXXX=====XXXX//		 x | A | B | C | D | i//// Timing:     Normal mode      Fast mode///////////////////////////////////////////////////////////////////////// Fscl        100KHz           400KHz// Th_scl      4.0us            0.6us   High period of SCL// Tl_scl      4.7us            1.3us   Low period of SCL// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition// Tsu:sto     4.0us            0.6us   setup time for a stop conditon// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition//// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "i2c_master_defines.v"module i2c_master_bit_ctrl(	clk, rst, nReset, 	clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,	scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen	);	//	// inputs & outputs	//	input clk;	input rst;	input nReset;	input ena;            // core enable signal	input [15:0] clk_cnt; // clock prescale value	input  [3:0] cmd;	output       cmd_ack; // command complete acknowledge	reg cmd_ack;	output       busy;    // i2c bus busy	reg busy;	output       al;      // i2c bus arbitration lost	reg al;	input  din;	output dout;	reg dout;	// I2C lines	input  scl_i;         // i2c clock line input	output scl_o;         // i2c clock line output	output scl_oen;       // i2c clock line output enable (active low)	reg scl_oen;	input  sda_i;         // i2c data line input	output sda_o;         // i2c data line output	output sda_oen;       // i2c data line output enable (active low)	reg sda_oen;	//	// variable declarations	//	reg sSCL, sSDA;             // synchronized SCL and SDA inputs	reg dscl_oen;               // delayed scl_oen	reg sda_chk;                // check SDA output (Multi-master arbitration)	reg clk_en;                 // clock generation signals	wire slave_wait;//	reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)	reg [15:0] cnt;             // clock divider counter (synthesis)	// state machine variable	reg [16:0] c_state; // synopsys enum_state	//	// module body	//	// whenever the slave is not ready it can delay the cycle by pulling SCL low	// delay scl_oen	always @(posedge clk)	  dscl_oen <= #1 scl_oen;
	  	//master release bus,and detect sSCL being pull low by slave	assign slave_wait = dscl_oen && !sSCL;	
		// generate clk enable signal	always @(posedge clk or negedge nReset)	  if(~nReset)	    begin	        cnt    <= #1 16'h0;		        clk_en <= #1 1'b1;		//clk enable once cnt be zero	    end	  else if (rst)	    begin	        cnt    <= #1 16'h0;	        clk_en <= #1 1'b1;	    end	  else if ( ~|cnt || !ena)	    begin	        cnt    <= #1 clk_cnt;	        clk_en <= #1 1'b1;	    end	  else if (slave_wait)	    begin	        cnt    <= #1 cnt;		//if slave wait,keep cnt	        clk_en <= #1 1'b0;    	    end	  else	    begin	        cnt    <= #1 cnt - 16'h1;	        clk_en <= #1 1'b0;	    end	// generate bus status controller	reg dSCL, dSDA;	reg sta_condition;	reg sto_condition;	// synchronize SCL and SDA inputs	// reduce metastability risc	always @(posedge clk or negedge nReset)	  if (~nReset)	    begin	        sSCL <= #1 1'b1;	        sSDA <= #1 1'b1;	        dSCL <= #1 1'b1;	        dSDA <= #1 1'b1;	    end	  else if (rst)	    begin	        sSCL <= #1 1'b1;	        sSDA <= #1 1'b1;	        dSCL <= #1 1'b1;	        dSDA <= #1 1'b1;	    end	  else	    begin	        sSCL <= #1 scl_i;	        sSDA <= #1 sda_i;	        dSCL <= #1 sSCL;			        dSDA <= #1 sSDA;	    end	// detect start condition => detect falling edge on SDA while SCL is high	// detect stop condition => detect rising edge on SDA while SCL is high	always @(posedge clk or negedge nReset)	  if (~nReset)	    begin	        sta_condition <= #1 1'b0;	        sto_condition <= #1 1'b0;	    end	  else if (rst)	    begin