;START_HEADER
;
; dsPIC30F6014 Demo Source File
; (c) Copyright 2005 Microchip Technology, All rights reserved
;
; --------------------------------------------------------------------------
; File Revision History:
; --------------------------------------------------------------------------
;
; $Log: init_spi2.s,v $
; Revision 1.3  2005/04/04 23:44:21  VasukiH
; Updates to comments in file header
;
; Revision 1.2  2005/04/04 23:15:55  VasukiH
; Updates for MPLAB C30 v1.30 compatiblity
;
; Revision 1.1.1.1  2003/08/23 00:38:32  VasukiH
; First import of demo source into CVS Repository
;
;
;
; --------------------------------------------------------------------------
;
; Software and Development Tools Info:
; --------------------------------------------------------------------------
; Tool                          Version
; --------------------------------------------------------------------------
; MPLAB IDE                     7.0
; MPLAB C30 Toolsuite           1.30
; dsPICDEM(TM) Processor Board  1.10
; --------------------------------------------------------------------------
;
; File Notes:
; This file contains two initialization routines for the SPI2 module:
; 1.  _init_spi2_A
; 2.  _init_spi2_B
; The dsPICDEM(TM) Controller board features two devices that communicate to
; the dsPIC30F via a shared SPI2 module on the dsPIC30F device. These are:
; - PIC18F242: LCD Controller
; - MCP41010:  Digital Potentiometer
;
; 1. _init_spi2_A Description:
; (i)   The SPI2 module is configured to communicate with the PIC18F242
;       on the board in an interrupt-driven fashion.
;       The 18F242 will control the LCD on the board.
; (ii)  The SPI2-PIC18F242 communication is controlled by the dsPIC30F (Master).
;       Data is transferred to and fro in Bytes at a clock rate of Fcy/8
;       i.e., approximately 921 KHz.
; (iii) The Slave Select pin on the dsPIC30F SPI2 module is used as a Chip Select
;       for the PIC18F242.
;
; 2. _init_spi2_B Description:
; (i)   The SPI2 module is configured to communicate with the MCP41010
;       on the board in a polling fashion.
; (ii)  The dsPIC30F sends the MCP41010 16-bit words which consist
;        of a control byte and an 8-bit PCM sine-sample.
; (ii)  The SPI2-PIC18F242 communication is controlled by the dsPIC30F (Master).
;       Data is transferred to and fro in Words at a clock rate of Fcy/32
;       i.e., approximately 230 KHz.
; (iv)  PORTD.RD7 is used to select the MCP41010.
;
;END_HEADER


.include "p30fxxxx.inc"

.global _init_spi2_A, _init_spi2_B

.section .text
_init_spi2_A:
        push    w0                      ; Save w0

        bset    LATG, #LATG9            ; Configure RG9 to be slave select
        bclr    TRISG, #TRISG9          ; signal for selecting PIC18f242

        clr     SPI2STAT
        mov     #0x001A, w0
        mov     w0, SPI2CON             ; Master Clk = Fcy/8 (using primary and
                                        ; secondary prescalers)

        bclr    SPI2CON, #SMP           ; Input data sampled at middle of output time
        bclr    SPI2CON, #CKE           ; data clocked out on rising edge

        bclr    SPI2CON, #CKP           ; CLK idle is low/Clock Active is High
        bset    SPI2CON, #MSTEN         ; SPI2 in Master mode

        bclr    SPI2STAT, #SPIROV       ; Clear any overflow errors

        bset    IPC6, #SPI2IP2
        bclr    IPC6, #SPI2IP1
        bset    IPC6, #SPI2IP0

        bclr    IFS1, #SPI2IF           ; Clear the interrupt flag bit
        bclr    IEC1, #SPI2IE           ; Disable SPI2 ISR processing for now
                                        ; This will be enabled later in source code

        bset    SPI2STAT, #SPIEN        ; Enable SPI2

        pop     w0                      ; Restore w0
        return                          ; Return to calling routine

_init_spi2_B:
        push    w0                      ; Save w0

        clr     SPI2STAT                ; Reset module to known state

        mov     #0x0002, w0             ; Master Clk = Fcy/32 (using primary and
        mov     w0, SPI2CON             ; secondary prescalers)

        bclr    SPI2CON, #SMP           ; Input data sampled at middle of output time
        bclr    SPI2CON, #CKP           ; Clock Idle = low, Active = high
        bset    SPI2CON, #CKE           ; Transmission on clock transition
                                        ; from Active to Idle

        bset    SPI2CON, #MODE16        ; Enable 16-bit mode
        bset    SPI2CON, #MSTEN         ; Enable Master mode

        bclr    IFS1, #SPI2IF
        bclr    IEC1, #SPI2IE

        bset    SPI2STAT, #SPIEN        ; enable SPI module


        pop     w0                      ; Restore w0
        return                          ; Return to calling routine
.end