?? segdis02.rpt
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Project Informatione:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 11/08/2005 09:24:29
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SEGDIS02
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
segdis01 EP1K30QC208-3 4 8 0 0 0 % 7 0 %
User Pins: 4 8 0
Project Informatione:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':2' stuck at GND
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K30QC208-3 are preliminary
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
***** Logic for device 'segdis01' compiled without errors.
Device: EP1K30QC208-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S V S S S S S S S S S S S S S V d S S S S S S S S S S S S S S S S S S S S S
E E E E E E E C E E E E E E V E E E E E E E C i E E V E E E E E E E E E E E V E E E E E E E E
R R R R R R R C R R R R R R C R R R R R R R C s R R C R R R R R R R R R R R C R R R R R R R R
V V V V V V V I V V V V V V C V V V V V G V V I G G i G V V C V V V V V V G V V V V V C V V V V V V V V
E E E E E E E N E E E E E E I E E E E E N E E N N N n N E E I E E E E E E N E E E E E I E E E E E E E E
D D D D D D D T D D D D D D O D D D D D D D D T D D 2 D D D O D D D D D D D D D D D D O D D D D D D D D
----------------------------------------------------------------------------------------------------------_
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
RESERVED | 7 150 | RESERVED
RESERVED | 8 149 | RESERVED
RESERVED | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
RESERVED | 16 141 | RESERVED
RESERVED | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | RESERVED
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K30QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
leddis2 | 36 121 | RESERVED
leddis4 | 37 120 | RESERVED
leddis1 | 38 119 | leddis3
leddis5 | 39 118 | VCCIO
leddis6 | 40 117 | GND
leddis0 | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R l V R R R G V d s d G G R V R R R R R R V R R R R R R V R R R R R R
E E E E E E N E E E E E E C E E E E e C E E E N C i c i N N E C E E E E E E C E E E E E E C E E E E E E
S S S S S S D S S S S S S C S S S S d C S S S D C s l s D D S C S S S S S S C S S S S S S C S S S S S S
E E E E E E E E E E E E I E E E E d I E E E I i k i E I E E E E E E I E E E E E E I E E E E E E
R R R R R R R R R R R R O R R R R i N R R R N n n R O R R R R R R N R R R R R R O R R R R R R
V V V V V V V V V V V V V V V V s T V V V T 1 0 V V V V V V V T V V V V V V V V V V V V
E E E E E E E E E E E E E E E E 7 E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
E26 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 8/141 ( 5%)
Total logic cells used: 7/1728 ( 0%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.71/4 ( 67%)
Total fan-in: 19/6912 ( 0%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 7
Total flipflops required: 7
Total packed registers required: 0
Total logic cells in carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 7/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 7/0
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - -- INPUT ^ 0 0 0 6 disin0
78 - - - -- INPUT ^ 0 0 0 6 disin1
182 - - - -- INPUT ^ 0 0 0 7 disin2
79 - - - -- INPUT G ^ 0 0 0 0 sclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
41 - - E -- OUTPUT 0 1 0 0 leddis0
38 - - E -- OUTPUT 0 1 0 0 leddis1
36 - - E -- OUTPUT 0 1 0 0 leddis2
119 - - E -- OUTPUT 0 1 0 0 leddis3
37 - - E -- OUTPUT 0 1 0 0 leddis4
39 - - E -- OUTPUT 0 1 0 0 leddis5
40 - - E -- OUTPUT 0 1 0 0 leddis6
71 - - - 21 OUTPUT 0 0 0 0 leddis7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
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