?? segdis02.rpt
字號:
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 26 DFFE + 2 0 1 0 :4
- 8 - E 26 DFFE + 3 0 1 0 :6
- 2 - E 26 DFFE + 2 0 1 0 :8
- 7 - E 26 DFFE + 3 0 1 0 :10
- 1 - E 26 DFFE + 3 0 1 0 :12
- 4 - E 26 DFFE + 3 0 1 0 :14
- 6 - E 26 DFFE + 3 0 1 0 :16
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 2/144( 1%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 sclk
Device-Specific Information:e:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
segdis01
** EQUATIONS **
disin0 : INPUT;
disin1 : INPUT;
disin2 : INPUT;
sclk : INPUT;
-- Node name is 'leddis0'
-- Equation name is 'leddis0', type is output
leddis0 = _LC6_E26;
-- Node name is 'leddis1'
-- Equation name is 'leddis1', type is output
leddis1 = _LC4_E26;
-- Node name is 'leddis2'
-- Equation name is 'leddis2', type is output
leddis2 = _LC1_E26;
-- Node name is 'leddis3'
-- Equation name is 'leddis3', type is output
leddis3 = _LC7_E26;
-- Node name is 'leddis4'
-- Equation name is 'leddis4', type is output
leddis4 = _LC2_E26;
-- Node name is 'leddis5'
-- Equation name is 'leddis5', type is output
leddis5 = _LC8_E26;
-- Node name is 'leddis6'
-- Equation name is 'leddis6', type is output
leddis6 = _LC5_E26;
-- Node name is 'leddis7'
-- Equation name is 'leddis7', type is output
leddis7 = GND;
-- Node name is ':4'
-- Equation name is '_LC5_E26', type is buried
_LC5_E26 = DFFE( _EQ001, GLOBAL( sclk), VCC, VCC, VCC);
_EQ001 = disin2
# disin1;
-- Node name is ':6'
-- Equation name is '_LC8_E26', type is buried
_LC8_E26 = DFFE( _EQ002, GLOBAL( sclk), VCC, VCC, VCC);
_EQ002 = disin2
# !disin0 & !disin1;
-- Node name is ':8'
-- Equation name is '_LC2_E26', type is buried
_LC2_E26 = DFFE( _EQ003, GLOBAL( sclk), VCC, VCC, VCC);
_EQ003 = !disin0 & !disin2;
-- Node name is ':10'
-- Equation name is '_LC7_E26', type is buried
_LC7_E26 = DFFE( _EQ004, GLOBAL( sclk), VCC, VCC, VCC);
_EQ004 = disin1
# disin0 & disin2
# !disin0 & !disin2;
-- Node name is ':12'
-- Equation name is '_LC1_E26', type is buried
_LC1_E26 = DFFE( _EQ005, GLOBAL( sclk), VCC, VCC, VCC);
_EQ005 = disin2
# !disin1
# disin0;
-- Node name is ':14'
-- Equation name is '_LC4_E26', type is buried
_LC4_E26 = DFFE( _EQ006, GLOBAL( sclk), VCC, VCC, VCC);
_EQ006 = !disin0 & !disin1
# !disin2;
-- Node name is ':16'
-- Equation name is '_LC6_E26', type is buried
_LC6_E26 = DFFE( _EQ007, GLOBAL( sclk), VCC, VCC, VCC);
_EQ007 = disin1
# !disin0 & !disin2
# disin0 & disin2;
Project Informatione:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis02.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,183K
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