-- Node name is 'leddis5' 
-- Equation name is 'leddis5', type is output 
leddis5  =  _LC1_C13;

-- Node name is 'leddis6' 
-- Equation name is 'leddis6', type is output 
leddis6  =  _LC3_C13;

-- Node name is 'leddis7' 
-- Equation name is 'leddis7', type is output 
leddis7  =  GND;

-- Node name is ':4' 
-- Equation name is '_LC3_C13', type is buried 
_LC3_C13 = DFFE( _EQ001, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ001 =  disin1 & !disin2
         # !disin1 &  disin2
         #  disin3
         # !disin0 &  disin1
         # !disin0 &  disin2;

-- Node name is ':6' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = DFFE( _EQ002, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ002 =  disin3
         # !disin1 &  disin2
         # !disin0 & !disin1
         # !disin0 &  disin2;

-- Node name is ':8' 
-- Equation name is '_LC6_C13', type is buried 
_LC6_C13 = DFFE( _EQ003, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC2_C13 &  _LC5_C13
         # !_LC2_C13 &  _LC7_C13
         #  _LC1_C9;

-- Node name is ':10' 
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = DFFE( _EQ004, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ004 = !_LC2_C13 &  _LC7_C9
         # !_LC2_C13 &  _LC3_C9
         #  _LC1_C9;

-- Node name is ':12' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = DFFE( _EQ005, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ005 =  disin3
         #  disin0
         # !disin1
         #  disin2;

-- Node name is ':14' 
-- Equation name is '_LC5_C9', type is buried 
_LC5_C9  = DFFE( _EQ006, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ006 =  _LC3_C9
         #  _LC6_C9
         #  _LC1_C9
         # !_LC2_C9;

-- Node name is ':16' 
-- Equation name is '_LC8_C9', type is buried 
_LC8_C9  = DFFE( _EQ007, GLOBAL( sclk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC1_C9
         #  _LC2_C9;

-- Node name is ':351' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ008);
  _EQ008 = !disin0 &  disin1 & !disin2 & !disin3;

-- Node name is ':363' 
-- Equation name is '_LC2_C13', type is buried 
!_LC2_C13 = _LC2_C13~NOT;
_LC2_C13~NOT = LCELL( _EQ009);
  _EQ009 =  disin3
         # !disin0
         #  disin1
         #  disin2;

-- Node name is ':375' 
-- Equation name is '_LC1_C9', type is buried 
_LC1_C9  = LCELL( _EQ010);
  _EQ010 = !disin0 & !disin1 & !disin2 & !disin3;

-- Node name is '~468~1' 
-- Equation name is '~468~1', location is LC7_C13, type is buried.
-- synthesized logic cell 
_LC7_C13 = LCELL( _EQ011);
  _EQ011 = !disin0 & !disin1 & !disin2 &  disin3
         # !disin0 &  disin1 &  disin2 & !disin3;

-- Node name is ':491' 
-- Equation name is '_LC7_C9', type is buried 
_LC7_C9  = LCELL( _EQ012);
  _EQ012 =  disin3
         # !disin2
         #  disin0 & !disin1
         # !disin0 &  disin1;

-- Node name is ':548' 
-- Equation name is '_LC6_C9', type is buried 
_LC6_C9  = LCELL( _EQ013);
  _EQ013 =  disin3
         # !disin2
         # !disin0 & !disin1
         #  disin0 &  disin1;

-- Node name is '~558~1' 
-- Equation name is '~558~1', location is LC3_C9, type is buried.
-- synthesized logic cell 
_LC3_C9  = LCELL( _EQ014);
  _EQ014 =  disin1 & !disin2 & !disin3;

-- Node name is ':590' 
-- Equation name is '_LC2_C9', type is buried 
_LC2_C9  = LCELL( _EQ015);
  _EQ015 =  disin3
         #  disin1
         #  disin0 &  disin2
         # !disin0 & !disin2;



Project Informatione:\pc-2lab2\maxplusii\max2work\vhdlwork\autoring\segdis.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,434K