#define fIISPSR_B       Fld(5, 0)       /* Prescaler Control B */#define IISPSR_B(x)     FInsrt((x), fIISPSR_B)  #define IISFCON_TX_NORM (0 << 15)       /* Transmit FIFO access mode: normal */#define IISFCON_TX_DMA  (1 << 15)       /* Transmit FIFO access mode: DMA */#define IISFCON_RX_NORM (0 << 14)       /* Receive FIFO access mode: normal */#define IISFCON_RX_DMA  (1 << 14)       /* Receive FIFO access mode: DMA */#define IISFCON_TX_EN   (1 << 13)        /* Transmit FIFO enable */#define IISFCON_RX_EN   (1 << 12)        /* Recevice FIFO enable */#define fIISFCON_TX_CNT Fld(6, 6)       /* Tx FIFO data count (Read-Only) */#define IISFCON_TX_CNT  FMsk(fIISFCON_TX_CNT)#define fIISFCON_RX_CNT Fld(6, 0)       /* Rx FIFO data count (Read-Only) */#define IISFCON_RX_CNT  FMsk(fIISFCON_RX_CNT)#define UD_FUNC_UD	(1 << 7)#define fUD_FUNC_ADDR	Fld(7,0)	/* USB Device Addr. assigned by host */#define UD_FUNC_ADDR	FMsk(fUD_FUNC_ADDR)#define UD_PWR_ISOUP	(1<<7) // R/W#define UD_PWR_RESET	(1<<3) // R#define UD_PWR_RESUME	(1<<2) // R/W#define UD_PWR_SUSPND	(1<<1) // R#define UD_PWR_ENSUSPND	(1<<0) // R/W#define UD_PWR_DEFAULT	0x00#define UD_INT_EP4	(1<<4)	// R/W (clear only)#define UD_INT_EP3	(1<<3)	// R/W (clear only)#define UD_INT_EP2	(1<<2)	// R/W (clear only)#define UD_INT_EP1	(1<<1)	// R/W (clear only)#define UD_INT_EP0	(1<<0)	// R/W (clear only)#define UD_USBINT_RESET	(1<<2) // R/W (clear only)#define UD_USBINT_RESUM	(1<<1) // R/W (clear only)#define UD_USBINT_SUSPND (1<<0) // R/W (clear only)#define UD_INTE_EP4	(1<<4) // R/W#define UD_INTE_EP3	(1<<3) // R/W#define UD_INTE_EP2	(1<<2) // R/W#define UD_INTE_EP1	(1<<1) // R/W#define UD_INTE_EP0	(1<<0) // R/W#define UD_USBINTE_RESET	(1<<2) // R/W#define UD_USBINTE_SUSPND	(1<<0) // R/W#define fUD_FRAMEL_NUM	Fld(8,0) // R#define UD_FRAMEL_NUM	FMsk(fUD_FRAMEL_NUM)#define fUD_FRAMEH_NUM	Fld(8,0) // R#define UD_FRAMEH_NUM	FMsk(fUD_FRAMEH_NUM)#define UD_INDEX_EP0	(0x00)#define UD_INDEX_EP1	(0x01) // ??#define UD_INDEX_EP2	(0x02) // ??#define UD_INDEX_EP3	(0x03) // ??#define UD_INDEX_EP4	(0x04) // ??#define UD_ICSR1_CLRDT	(1<<6)   // R/W#define UD_ICSR1_SENTSTL (1<<5)  // R/W (clear only)#define UD_ICSR1_SENDSTL (1<<4)  // R/W#define UD_ICSR1_FFLUSH (1<<3)  // W	(set only)#define UD_ICSR1_UNDRUN  (1<<2)  // R/W (clear only)#define UD_ICSR1_PKTRDY	 (1<<0)  // R/W (set only)#define UD_ICSR2_AUTOSET (1<<7) // R/W#define UD_ICSR2_ISO	 (1<<6)	// R/W#define UD_ICSR2_MODEIN	 (1<<5) // R/W#define UD_ICSR2_DMAIEN	 (1<<4) // R/W#define UD_OCSR1_CLRDT	(1<<7) // R/W#define UD_OCSR1_SENTSTL	(1<<6)	// R/W (clear only)#define UD_OCSR1_SENDSTL	(1<<5)	// R/W#define UD_OCSR1_FFLUSH		(1<<4) // R/W#define UD_OCSR1_DERROR		(1<<3) // R#define UD_OCSR1_OVRRUN		(1<<2) // R/W (clear only)#define UD_OCSR1_PKTRDY		(1<<0) // R/W (clear only)#define UD_OCSR2_AUTOCLR	(1<<7) // R/W#define UD_OCSR2_ISO		(1<<6) // R/W#define UD_OCSR2_DMAIEN		(1<<5) // R/W#define fUD_FIFO_DATA	Fld(8,0) // R/W#define UD_FIFO0_DATA	FMsk(fUD_FIFO_DATA)#define UD_FIFO1_DATA	FMsk(fUD_FIFO_DATA)#define UD_FIFO2_DATA	FMsk(fUD_FIFO_DATA)#define UD_FIFO3_DATA	FMsk(fUD_FIFO_DATA)#define UD_FIFO4_DATA	FMsk(fUD_FIFO_DATA)#define UD_MAXP_8	(1<<0)#define UD_MAXP_16	(1<<1)#define UD_MAXP_32	(1<<2)#define UD_MAXP_64	(1<<3)#define fUD_OFCNT_DATA	Fld(8,0)#define UD_OFCNTL_DATA	FMsk(fUD_OFCNT_DATA) //R#define UD_OFCNTH_DATA	FMsk(fUD_OFCNT_DATA) //R#define UD_DMACONx_INRUNOB	(1<<7) // R#define fUD_DMACON_STATE	Fld(3,4) // R#define UD_DMACONx_STATE	FMsk(fUD_DMACON_STATE) // R/W#define UD_DMACONx_DEMEN	(1<<3) // R/W#define UD_DMACONx_ORUN		(1<<2) // R/W#define UD_DMACONx_IRUN		(1<<1) // R/W#define UD_DMACONx_DMAMODE	(1<<0) // R/W#define fUD_DMAUC_DATA	Fld(8,0)#define UD_DMAUCx_DATA	FMsk(fUD_DMAUC_DATA)#define fUD_DMAFC_DATA	Fld(8,0)#define UD_DMAFCx_DATA	FMsk(fUD_DMAFC_DATA)#define fUD_DMATC_DATA	Fld(8,0)#define UD_DMATCL_DATA	FMsk(fUD_DMATC_DATA)#define UD_DMATCM_DATA	FMsk(fUD_DMATC_DATA)#define UD_DMATCH_DATA	FMsk(fUD_DMATC_DATA)#define EP0_CSR_OPKRDY	(1<<0)#define EP0_CSR_IPKRDY	(1<<1)#define EP0_CSR_SENTSTL	(1<<2)#define EP0_CSR_DE	(1<<3)#define EP0_CSR_SE	(1<<4)#define EP0_CSR_SENDSTL	(1<<5)#define EP0_CSR_SOPKTRDY (1<<6)#define EP0_CSR_SSE	(1<<7)#define fSPCON_SMOD	Fld(2,5)	/* SPI Mode Select */#define SPCON_SMOD	FMsk(fSPCON_SMOD)#define SPCON_SMOD_POLL	FInsrt(0x0, fSPCON_SMOD)	/* polling mode */#define SPCON_SMOD_INT	FInsrt(0x1, fSPCON_SMOD)	/* interrupt mode */#define SPCON_SMOD_DMA	FInsrt(0x2, fSPCON_SMOD)	/* DMA mode */#define SPCON_ENSCK	(1 << 4)	/* Enable SCK */#define SPCON_MSTR	(1 << 3)	/* Master/Slave select					   0: slave, 1: master */#define SPCON_CPOL	(1 << 2)	/* Clock polarity select					   1: active low, 0: active high */#define SPCON_CPOL_LOW	(1 << 2)#define SPCON_CPOL_HIGH	(0 << 2)#define SPCON_CPHA	(1 << 1)	/* Clock Phase Select					   0: format A, 1: format B */#define SPCON_CPHA_FMTA	(0 << 1)#define SPCON_CPHA_FMTB	(1 << 1)#define SPCON_TAGD	(1 << 0)	/* Tx auto garbage data mode enable			in normal mode, you only want to receive data,					you should tranmit dummy 0xFF data */#define SPSTA_DCOL	(1 << 2)	/* Data Collision Error */#define SPSTA_MULF	(1 << 1)	/* Multi Master Error */#define SPSTA_READY	(1 << 0)	/* data Tx/Rx ready */#define SPPIN_ENMUL	(1 << 2)	/* Multi Master Error detect Enable */#define SPPIN_KEEP	(1 << 0)	/* Master Out keep */#define SDICON_BYTE	(1 << 4)	/* Byte Order Type */#define SDICON_LE	(0 << 4)	/* D[7:0],D[15:8],D[23:16],D[31:24] */#define SDICON_BE	(1 << 4)	/* D[31:24],D[23:16],D[15:8],D[7:0] */#define SDICON_INT	(1 << 3)	/* Receive SDIO INterrupt from card */#define SDICON_RWE	(1 << 2)	/* Read Wait Enable */#define SDICON_FRESET	(1 << 1)	/* FIFO Reset */#define SDICON_ENCLK	(1 << 0)	/* Clock Out Enable */#define SDIPRE_MSK	(0xff)		/* Baud rate = PCLK/2/(value + 1) */#define SDICCON_ABORT	(1 << 12)	/* Command type: Abort(CMD12,CMD52) */#define SDICCON_DATA	(1 << 11)	/* Command type: with Data */#define SDICCON_LRSP	(1 << 10)	/* Response is 136-bit long */#define SDICCON_WRSP	(1 << 9)	/* Wait for Response */#define SDICCON_START	(1 << 8)	/* 0: cmd ready, 1: cmd start */#define SDICCON_CMD_MSK	(0xff)		/* with start 2bit */#define SDICSTA_CRC	(1 << 12)	/* CRC error */#define SDICSTA_SENT	(1 << 11)	/* Command sent */#define SDICSTA_TOUT	(1 << 10)	/* Command Timeout */#define SDICSTA_RSP	(1 << 9)	/* Command Response received */#define SDICSTA_BUSY	(1 << 8)	/* Command transfer in progress */#define SDICSTA_ALLFLAG	(0x1f00)	/* All flags mask */#define SDICSTA_RSP_MSK	(0xff)		/* with start 2bit */#define SDICSTA_ERR	(0x1400)	/* CRC, TOUT */#define SDIRSP1_CRC7	FExtr(SDIRSP1, Fld(8,24))#define SDIDCON_PRD	(1 << 21)	/* SDIO Interrupt period is ... */				/* when last data block is transferred. */#define SDIDCON_PRD_2	(0 << 21)	/* 0: exact 2 cycle */#define SDIDCON_PRD_N	(1 << 21)	/* 1: more cycle */#define SDIDCON_TARSP	(1 << 20)	/* when data transmit start ... */#define SDIDCON_TARSP_0	(0 << 20)	/* 0: directly after DatMode set */#define SDIDCON_TARSP_1	(1 << 20)	/* 1: after response receive */#define SDIDCON_RACMD	(1 << 19)	/* when data receive start ... */#define SDIDCON_RACMD_0	(0 << 19)	/* 0: directly after DatMode set */#define SDIDCON_RACMD_1	(1 << 19)	/* 1: after command sent */#define SDIDCON_BACMD	(1 << 18)	/* when busy receive start ... */#define SDIDCON_BACMD_0	(0 << 18)	/* 0: directly after DatMode set */#define SDIDCON_BACMD_1	(1 << 18)	/* 1: after command sent */#define SDIDCON_BLK	(1 << 17)	/* transfer mode. 0:stream, 1:block */#define SDIDCON_WIDE	(1 << 16)	/* Enable Wide bus mode */#define SDIDCON_DMA	(1 << 15)	/* Enable DMA */#define SDIDCON_STOP	(1 << 14)	/* Stop by force */#define fSDIDCON_DatMode Fld(2,12)	/* which direction of data transfer */#define SDIDCON_READY	FInsrt(0x0, fSDIDCON_DatMode)	/* ready */#define SDIDCON_BUSY	FInsrt(0x1, fSDIDCON_DatMode)	/* only busy check */#define SDIDCON_RX	FInsrt(0x2, fSDIDCON_DatMode)	/* Data receive */#define SDIDCON_TX	FInsrt(0x3, fSDIDCON_DatMode)	/* Data transmit */#define SDIDCON_BNUM	FMsk(Fld(12,0))	/* Block Number(0~4095) */#define SDIDCNT_CNT(x)	FExtr((x), Fld(12,12))	/* Remaining Blk No. */#define SDIDCNT_SIZE(x)	FExtr((x), Fld(12,0))	/* Remaining byte of 1 block */#define SDIDSTA_RWQ	(1 << 10)	/* Read wait request occur */#define SDIDSTA_INT	(1 << 9)	/* SDIO interrupt detect */#define SDIDSTA_EFIFO	(1 << 8)	/* FIFO fail */#define SDIDSTA_ETCRC	(1 << 7)	/* Block sent(CRC status error) */#define SDIDSTA_ERCRC	(1 << 6)	/* Block received(CRC error) */#define SDIDSTA_TOUT	(1 << 5)	/* Data/Busy receive timeout */#define SDIDSTA_DFIN	(1 << 4)	/* Data transfer complete */#define SDIDSTA_BFIN	(1 << 3)	/* Only busy check is finished */#define SDIDSTA_SBIT	(1 << 2)	/* Start bit is not detected */#define SDIDSTA_TX	(1 << 1)	/* data Tx in progress */#define SDIDSTA_RX	(1 << 0)	/* data Rx in progress */#define SDIDSTA_ERR	(0x1e4)		/* EFIFO, ETCRC, ERCRC, TOUT, SBIT */#define fSDIDSTA_ALL	Fld(11, 0)#define SDIDSTA_ALL	FMsk(fSDIDSTA_ALL)#define SDIFSTA_TX	(1 << 13)	/* 0: FIFO is full, 1: FIFO ready */#define SDIFSTA_RX	(1 << 12)	/* 0: FIFO empty, 1: Data in FIFO */#define SDIFSTA_TX_HALF	(1 << 11)	/* Data in FIFO are 0:33~64, 1:0~32 */#define SDIFSTA_TX_EMP	(1 << 10)	/* FIFO is empty */#define SDIFSTA_RX_LAST	(1 << 9)	/* Last Data ready in FIFO */#define SDIFSTA_RX_FULL	(1 << 8)	/* FIFO is full */#define SDIFSTA_RX_HALF	(1 << 7)	/* Data in FIFO are 0:0~31, 1:32~64 */#define SDIFSTA_CNT	(0x7f)		/* Number of data in FIFO */#define SDIIMSK_RCRC	(1 << 17)	/* Response CRC error */#define SDIIMSK_CSENT	(1 << 16)	/* Command Sent */#define SDIIMSK_CTOUT	(1 << 15)	/* Command Response Timeout */#define SDIIMSK_CRSP	(1 << 14)	/* Command Response received */#define SDIIMSK_RWAIT	(1 << 13)	/* Read Wait Request */#define SDIIMSK_CARD	(1 << 12)	/* SDIO Interrupt from card */#define SDIIMSK_EFIFO	(1 << 11)	/* FIFO fail error */#define SDIIMSK_ETCRC	(1 << 10)	/* CRC status error */#define SDIIMSK_ERCRC	(1 << 9)	/* Data CRC fail */#define SDIIMSK_TOUT	(1 << 8)	/* Data Timeout */#define SDIIMSK_DFIN	(1 << 7)	/* Data transfer complete (cnt = 0) */#define SDIIMSK_BFIN	(1 << 6)	/* Busy check complete */#define SDIIMSK_SBIT	(1 << 5)	/* Start bit Error */#define SDIIMSK_TX_HALF	(1 << 4)	/* Tx FIFO half */#define SDIIMSK_TX_EMP	(1 << 3)	/* Tx FIFO empty */#define SDIIMSK_RX_LAST	(1 << 2)	/* Rx FIFO has last data */#define SDIIMSK_RX_FULL	(1 << 1)	/* Rx FIFO full */#define SDIIMSK_RX_HALF	(1 << 0)	/* Rx FIFO half */#define SDIIMSK_ALL	(0x3ffff)#define SDI_MAX_TX_FIFO	64#define SDI_MAX_RX_FIFO	64#define GPIO_SDDAT3	GPIO_E10#define GPIO_SDDAT2	GPIO_E9#define GPIO_SDDAT1	GPIO_E8#define GPIO_SDDAT0	GPIO_E7#define GPIO_SDCMD	GPIO_E6#define GPIO_SDCLK	GPIO_E5/* * Power Management */#define PMST            GSTATUS2#define PMSR0           GSTATUS3#define PMSR1           GSTATUS4#define PMCTL0          CLKCON  #define PMCTL1          MISCCR  #define SCLKE           (1 << 19)#define SCLK1           (1 << 18)#define SCLK0           (1 << 17)#define USBSPD1         (1 << 13)#define USBSPD0         (1 << 12)#define PMST_WDR        (1 << 2)#define PMST_SMR        (1 << 1)#define PMST_HWR        (1 << 0)/* * Watchdog timer */#define bWTCON(Nb)	__REG(0x53000000 + (Nb))#define WTCON		bWTCON(0)#define WTDAT		bWTCON(4)#define WTCNT		bWTCON(8)#endif // _S3C2410_H_/* | $Id: linuette_common.h,v 1.3 2002/05/10 15:52:08 tolkien Exp $ | | Local Variables: | mode: c | mode: font-lock | version-control: t | delete-old-versions: t | End: | | -*- End-Of-File -*- */