-------------------------------------------------------------------------------- lcd_ip.vhd - entity/architecture pair-------------------------------------------------------------------------------- IMPORTANT:-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.---- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.---- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION-- OF THE USER_LOGIC ENTITY.---------------------------------------------------------------------------------- ***************************************************************************-- ** Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.            **-- **                                                                       **-- ** Xilinx, Inc.                                                          **-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **-- ** FOR A PARTICULAR PURPOSE.                                             **-- **                                                                       **-- ***************************************************************************---------------------------------------------------------------------------------- Filename:          lcd_ip.vhd-- Version:           1.00.a-- Description:       Top level design, instantiates IPIF and user logic.-- Date:              Tue Nov 18 16:07:08 2008 (by Create and Import Peripheral Wizard)-- VHDL Standard:     VHDL'93-------------------------------------------------------------------------------- Naming Conventions:--   active low signals:                    "*_n"--   clock signals:                         "clk", "clk_div#", "clk_#x"--   reset signals:                         "rst", "rst_n"--   generics:                              "C_*"--   user defined types:                    "*_TYPE"--   state machine next state:              "*_ns"--   state machine current state:           "*_cs"--   combinatorial signals:                 "*_com"--   pipelined or register delay signals:   "*_d#"--   counter signals:                       "*cnt*"--   clock enable signals:                  "*_ce"--   internal version of output port:       "*_i"--   device pins:                           "*_pin"--   ports:                                 "- Names begin with Uppercase"--   processes:                             "*_PROCESS"--   component instantiations:              "<ENTITY_>I_<#|FUNC>"------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;library proc_common_v2_00_a;use proc_common_v2_00_a.proc_common_pkg.all;use proc_common_v2_00_a.ipif_pkg.all;library opb_ipif_v3_01_c;use opb_ipif_v3_01_c.all;library lcd_ip_v1_00_a;use lcd_ip_v1_00_a.all;-------------------------------------------------------------------------------- Entity section-------------------------------------------------------------------------------- Definition of Generics:--   C_BASEADDR                   -- User logic base address--   C_HIGHADDR                   -- User logic high address--   C_OPB_AWIDTH                 -- OPB address bus width--   C_OPB_DWIDTH                 -- OPB data bus width--   C_FAMILY                     -- Target FPGA architecture---- Definition of Ports:--   OPB_Clk                      -- OPB Clock--   OPB_Rst                      -- OPB Reset--   Sl_DBus                      -- Slave data bus--   Sl_errAck                    -- Slave error acknowledge--   Sl_retry                     -- Slave retry--   Sl_toutSup                   -- Slave timeout suppress--   Sl_xferAck                   -- Slave transfer acknowledge--   OPB_ABus                     -- OPB address bus--   OPB_BE                       -- OPB byte enable--   OPB_DBus                     -- OPB data bus--   OPB_RNW                      -- OPB read/not write--   OPB_select                   -- OPB select--   OPB_seqAddr                  -- OPB sequential address------------------------------------------------------------------------------entity lcd_ip is  generic  (    -- ADD USER GENERICS BELOW THIS LINE ---------------    --USER generics added here    -- ADD USER GENERICS ABOVE THIS LINE ---------------    -- DO NOT EDIT BELOW THIS LINE ---------------------    -- Bus protocol parameters, do not add to or delete    C_BASEADDR                     : std_logic_vector     := X"00000000";    C_HIGHADDR                     : std_logic_vector     := X"0000FFFF";    C_OPB_AWIDTH                   : integer              := 32;    C_OPB_DWIDTH                   : integer              := 32;    C_FAMILY                       : string               := "virtex2p"    -- DO NOT EDIT ABOVE THIS LINE ---------------------  );  port  (    -- ADD USER PORTS BELOW THIS LINE ------------------    --USER ports added here	 lcd : out std_logic_vector (0 to 6);    -- ADD USER PORTS ABOVE THIS LINE ------------------    -- DO NOT EDIT BELOW THIS LINE ---------------------    -- Bus protocol ports, do not add to or delete    OPB_Clk                        : in  std_logic;    OPB_Rst                        : in  std_logic;    Sl_DBus                        : out std_logic_vector(0 to C_OPB_DWIDTH-1);    Sl_errAck                      : out std_logic;    Sl_retry                       : out std_logic;    Sl_toutSup                     : out std_logic;    Sl_xferAck                     : out std_logic;    OPB_ABus                       : in  std_logic_vector(0 to C_OPB_AWIDTH-1);    OPB_BE                         : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);    OPB_DBus                       : in  std_logic_vector(0 to C_OPB_DWIDTH-1);    OPB_RNW                        : in  std_logic;    OPB_select                     : in  std_logic;    OPB_seqAddr                    : in  std_logic    -- DO NOT EDIT ABOVE THIS LINE ---------------------  );  attribute SIGIS : string;  attribute SIGIS of OPB_Clk       : signal is "Clk";  attribute SIGIS of OPB_Rst       : signal is "Rst";end entity lcd_ip;-------------------------------------------------------------------------------- Architecture section------------------------------------------------------------------------------architecture IMP of lcd_ip is  ------------------------------------------  -- Constant: array of address range identifiers  ------------------------------------------  constant ARD_ID_ARRAY                   : INTEGER_ARRAY_TYPE   :=     (      0  => USER_00                           -- user logic S/W register address space    );  ------------------------------------------  -- Constant: array of address pairs for each address range  ------------------------------------------  constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 64-C_OPB_AWIDTH-1) := (others => '0');  constant USER_BASEADDR  : std_logic_vector  := C_BASEADDR;  constant USER_HIGHADDR  : std_logic_vector  := C_HIGHADDR;  constant ARD_ADDR_RANGE_ARRAY           : SLV64_ARRAY_TYPE     :=     (      ZERO_ADDR_PAD & USER_BASEADDR,              -- user logic base address      ZERO_ADDR_PAD & USER_HIGHADDR               -- user logic high address    );  ------------------------------------------  -- Constant: array of data widths for each target address range  ------------------------------------------  constant USER_DWIDTH                    : integer              := 32;  constant ARD_DWIDTH_ARRAY               : INTEGER_ARRAY_TYPE   :=     (      0  => USER_DWIDTH                       -- user logic data width    );  ------------------------------------------  -- Constant: array of desired number of chip enables for each address range  ------------------------------------------  constant USER_NUM_CE                    : integer              := 1;  constant ARD_NUM_CE_ARRAY               : INTEGER_ARRAY_TYPE   :=     (      0  => pad_power2(USER_NUM_CE)           -- user logic number of CEs    );  ------------------------------------------  -- Constant: array of unique properties for each address range  ------------------------------------------  constant ARD_DEPENDENT_PROPS_ARRAY      : DEPENDENT_PROPS_ARRAY_TYPE :=     (      0  => (others => 0)                     -- user logic slave space dependent properties (none defined)    );  ------------------------------------------  -- Constant: pipeline mode  -- 1 = include OPB-In pipeline registers  -- 2 = include IP pipeline registers  -- 3 = include OPB-In and IP pipeline registers  -- 4 = include OPB-Out pipeline registers