?? spmc75f2313a.inc
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// =========================================================================
// The information contained herein is the exclusive property of
// Sunplus Technology Co. And shall not be distributed, reproduced,
// or disclosed in whole in part without prior written permission.
// (C) COPYRIGHT 2001 SUNPLUS TECHNOLOGY CO.
// ALL RIGHTS RESERVED
// The entire notice above must be reproduced on all authorized copies.
// =========================================================================
// File Name : spmc75f2313a.inc
// Description : SPMC75F2313A register definition
// Processor : SPMC75X series
// Author : Chih ming Huang
// Tools : u'nSP IDE tools v1.18.1A or later version
// Version : 1.00
// Security : Confidential Proprietary
// E-Mail : MaxHuang@sunplus.com.tw
// =========================================================================
//***************************************************************************//
//***************************************************************************//
// A. CPU control register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_System_Option 0x8000
.DEFINE P_Wait_Enter 0x700C
.DEFINE P_Stdby_Enter 0x700E
.DEFINE P_Reset_Status 0x7006
.DEFINE P_Clk_Ctrl 0x7007
.DEFINE P_WatchDog_Ctrl 0x700A
.DEFINE P_WatchDog_Clr 0x700B
.DEFINE P_Wakeup_Ctrl 0x700F
.DEFINE P_INT_Status 0x70A0
.DEFINE P_INT_Priority 0x70A4
.DEFINE P_MisINT_Ctrl 0x70A8
//***************************************************************************//
//***************************************************************************//
// B. I/O Port register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_IOA_Data 0x7060
.DEFINE P_IOA_Buffer 0x7061
.DEFINE P_IOA_Dir 0x7062
.DEFINE P_IOA_Attrib 0x7063
.DEFINE P_IOA_Latch 0x7064
.DEFINE P_IOA_SPE 0x7080
.DEFINE P_IOA_KCER 0x7084
.DEFINE P_IOB_Data 0x7068
.DEFINE P_IOB_Buffer 0x7069
.DEFINE P_IOB_Dir 0x706A
.DEFINE P_IOB_Attrib 0x706B
.DEFINE P_IOB_Latch 0x706C
.DEFINE P_IOB_SPE 0x7081
.DEFINE P_IOC_Data 0x7070
.DEFINE P_IOC_Buffer 0x7071
.DEFINE P_IOC_Dir 0x7072
.DEFINE P_IOC_Attrib 0x7073
.DEFINE P_IOC_Latch 0x7074
.DEFINE P_IOC_SPE 0x7082
.DEFINE P_IOD_Data 0x7078
.DEFINE P_IOD_Buffer 0x7079
.DEFINE P_IOD_Dir 0x707A
.DEFINE P_IOD_Attrib 0x707B
//***************************************************************************//
//***************************************************************************//
// C. Timer 0,Timer 1,Timer 2,Timer 3,Timer 4 //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_TMR0_Ctrl 0x7400
.DEFINE P_TMR1_Ctrl 0x7401
.DEFINE P_TMR2_Ctrl 0x7402
.DEFINE P_TMR4_Ctrl 0x7404
.DEFINE P_TMR_LDOK 0x740A
.DEFINE P_TMR0_TCNT 0x7430
.DEFINE P_TMR1_TCNT 0x7431
.DEFINE P_TMR2_TCNT 0x7432
.DEFINE P_TMR4_TCNT 0x7434
.DEFINE P_TMR0_TGRA 0x7440
.DEFINE P_TMR0_TGRB 0x7441
.DEFINE P_TMR0_TGRC 0x7442
.DEFINE P_TMR1_TGRA 0x7443
.DEFINE P_TMR1_TGRB 0x7444
.DEFINE P_TMR1_TGRC 0x7445
.DEFINE P_TMR2_TGRA 0x7446
.DEFINE P_TMR2_TGRB 0x7447
.DEFINE P_TMR4_TGRA 0x744C
.DEFINE P_TMR4_TGRB 0x744D
.DEFINE P_TMR4_TGRC 0x744E
.DEFINE P_TMR4_TGRD 0x744F
.DEFINE P_TMR0_TPR 0x7435
.DEFINE P_TMR1_TPR 0x7436
.DEFINE P_TMR2_TPR 0x7437
.DEFINE P_TMR4_TPR 0x7439
.DEFINE P_TMR0_TBRA 0x7450
.DEFINE P_TMR0_TBRB 0x7451
.DEFINE P_TMR0_TBRC 0x7452
.DEFINE P_TMR1_TBRA 0x7453
.DEFINE P_TMR1_TBRB 0x7454
.DEFINE P_TMR1_TBRC 0x7455
.DEFINE P_TMR2_TBRA 0x7456
.DEFINE P_TMR2_TBRB 0x7457
.DEFINE P_TMR4_TBRA 0x745C
.DEFINE P_TMR4_TBRB 0x745D
.DEFINE P_TMR4_TBRC 0x745E
.DEFINE P_TMR0_IOCtrl 0x7410
.DEFINE P_TMR1_IOCtrl 0x7411
.DEFINE P_TMR2_IOCtrl 0x7412
.DEFINE P_TMR4_IOCtrl 0x7414
.DEFINE P_TMR0_INT 0x7420
.DEFINE P_TMR1_INT 0x7421
.DEFINE P_TMR2_INT 0x7422
.DEFINE P_TMR4_INT 0x7424
.DEFINE P_TMR0_Status 0x7425
.DEFINE P_TMR1_Status 0x7426
.DEFINE P_TMR2_Status 0x7427
.DEFINE P_TMR4_Status 0x7429
.DEFINE P_TMR_Start 0x7405
.DEFINE P_TMR_Output 0x7406
.DEFINE P_TMR4_OutputCtrl 0x7408
.DEFINE P_POS1_DectCtrl 0x7463
.DEFINE P_POS1_DectData 0x7465
.DEFINE P_TMR4_DeadTime 0x7461
.DEFINE P_TPWM_Write 0x7409
.DEFINE P_Fault2_Ctrl 0x7467
.DEFINE P_OL2_Ctrl 0x7469
.DEFINE P_Fault2_Release 0x746B
//***************************************************************************//
//***************************************************************************//
// D. 10-bit ADC converter register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_ADC_Setup 0x7160
.DEFINE P_ADC_Ctrl 0x7161
.DEFINE P_ADC_Data 0x7162
.DEFINE P_ADC_Channel 0x7166
//***************************************************************************//
//***************************************************************************//
// E. Standard Peripheral Interface SPI register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_SPI_Ctrl 0x7140
.DEFINE P_SPI_TxStatus 0x7141
.DEFINE P_SPI_TxBuf 0x7142
.DEFINE P_SPI_RxStatus 0x7143
.DEFINE P_SPI_RxBuf 0x7144
//***************************************************************************//
//***************************************************************************//
// F. Flash organization and control register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_Flash_RW 0x7554
.DEFINE P_Flash_Cmd 0x7555
//***************************************************************************//
//***************************************************************************//
// G. UART Control Register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_UART_Data 0x7100
.DEFINE P_UART_RXStatus 0x7101
.DEFINE P_UART_Ctrl 0x7102
.DEFINE P_UART_BaudRate 0x7103
.DEFINE P_UART_Status 0x7104
//***************************************************************************//
//***************************************************************************//
// H. Compare Match Timer Register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_CMT_Start 0x7500
.DEFINE P_CMT_Ctrl 0x7501
.DEFINE P_CMT0_TCNT 0x7508
.DEFINE P_CMT1_TCNT 0x7509
.DEFINE P_CMT0_TPR 0x7510
.DEFINE P_CMT1_TPR 0x7511
//***************************************************************************//
//***************************************************************************//
// I. Time Base Register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_TMB_Reset 0x70B8
//***************************************************************************//
//***************************************************************************//
//Constant Definition //
//***************************************************************************//
//***************************************************************************//
//=================================//
// Generic Port register //
//=================================//
// bit set //
.DEFINE CB_BIT0 0
.DEFINE CB_BIT1 1
.DEFINE CB_BIT2 2
.DEFINE CB_BIT3 3
.DEFINE CB_BIT4 4
.DEFINE CB_BIT5 5
.DEFINE CB_BIT6 6
.DEFINE CB_BIT7 7
.DEFINE CB_BIT8 8
.DEFINE CB_BIT9 9
.DEFINE CB_BIT10 10
.DEFINE CB_BIT11 11
.DEFINE CB_BIT12 12
.DEFINE CB_BIT13 13
.DEFINE CB_BIT14 14
.DEFINE CB_BIT15 15
//=================================//
// flash control register //
//=================================//
// P_Wait_Enter register //
// word set //
.DEFINE CW_WaitCMD 0x5005
.DEFINE CW_WaitClr 0x0001
// P_Stdby_Enter register //
// word set //
.DEFINE CW_StdbyCMD 0xA00A
.DEFINE CW_StdbyClr 0x0001
// P_System_Option register //
// word set //
.DEFINE CW_SYS_CLK_R 0x0000
.DEFINE CW_SYS_CLK_OSC 0x0001
.DEFINE CW_SYS_WDG_Disable (0x0000 << 1)
.DEFINE CW_SYS_WDG_Enable (0x0001 << 1)
.DEFINE CW_SYS_LVR_Disable (0x0000 << 2)
.DEFINE CW_SYS_LVR_Enable (0x0001 << 2)
.DEFINE CW_SYS_LVD_Disable (0x0000 << 3)
.DEFINE CW_SYS_LVD_Enable (0x0001 << 3)
.DEFINE CW_SYS_Security_Protect (0x0000 << 4)
.DEFINE CW_SYS_Security_NoProtect (0x0001 << 4)
.DEFINE CW_SYS_Verification (0x02AA << 5)
// Bit set //
.DEFINE CB_SYS_CLK 0
.DEFINE CB_SYS_WDG 1
.DEFINE CB_SYS_LVR 2
.DEFINE CB_SYS_LVD 3
.DEFINE CB_SYS_Security 4
.DEFINE CB_SYS_Verification0 5
.DEFINE CB_SYS_Verification1 6
.DEFINE CB_SYS_Verification2 7
.DEFINE CB_SYS_Verification3 8
.DEFINE CB_SYS_Verification4 9
.DEFINE CB_SYS_Verification5 10
.DEFINE CB_SYS_Verification6 11
.DEFINE CB_SYS_Verification7 12
.DEFINE CB_SYS_Verification8 13
.DEFINE CB_SYS_Verification9 14
.DEFINE CB_SYS_Verification10 15
// P_Reset_Status register //
// word set //
.DEFINE CW_CLEAR_EXTRF 0x0001
.DEFINE CW_CLEAR_PORF (0x0001 << 1)
.DEFINE CW_CLEAR_WDRF (0x0001 << 2)
.DEFINE CW_CLEAR_LPLVRF (0x0001 << 3)
.DEFINE CW_CLEAR_SPLVRF (0x0001 << 4)
.DEFINE CW_CLEAR_IARF (0x0001 << 5)
.DEFINE CW_CLEAR_IIRF (0x0001 << 6)
.DEFINE CW_CLEAR_FCHK (0x0055 << 9)
// Bit set //
.DEFINE CB_CLEAR_EXTRF 0
.DEFINE CB_CLEAR_PORF 1
.DEFINE CB_CLEAR_WDRF 2
.DEFINE CB_CLEAR_LVRF 3
.DEFINE CB_CLEAR_IARF 5
.DEFINE CB_CLEAR_IIRF 6
.DEFINE CB_CLEAR_FCHK0 8
.DEFINE CB_CLEAR_FCHK1 9
.DEFINE CB_CLEAR_FCHK2 10
.DEFINE CB_CLEAR_FCHK3 11
.DEFINE CB_CLEAR_FCHK4 12
.DEFINE CB_CLEAR_FCHK5 13
.DEFINE CB_CLEAR_FCHK6 14
.DEFINE CB_CLEAR_FCHK7 15
// P_Clk_Ctrl register //
// word set //
.DEFINE CW_CLK_OSCIE (0x0001 << 14)
.DEFINE CW_CLK_OSCSF (0x0001 << 15)
// Bit set //
.DEFINE CB_CLK_OSCIE 14
.DEFINE CB_CLK_OSCSF 15
// P_WatchDog_Ctrl register //
// word set //
.DEFINE CW_WDPS_FCKdiv65536 0x0000
.DEFINE CW_WDPS_FCKdiv32768 0x0001
.DEFINE CW_WDPS_FCKdiv16384 0x0002
.DEFINE CW_WDPS_FCKdiv8192 0x0003
.DEFINE CW_WDPS_FCKdiv4096 0x0004
.DEFINE CW_WDPS_FCKdiv2048 0x0005
.DEFINE CW_WDPS_FCKdiv1024 0x0006
.DEFINE CW_WDPS_FCKdiv512 0x0007
.DEFINE CW_WDCHK_Setting (0x0015 << 3)
.DEFINE CW_WDRS_SYS_Reset (0x0000 << 14)
.DEFINE CW_WDRS_CPU_Reset (0x0001 << 14)
.DEFINE CW_WDEN (0x0001 << 15)
.DEFINE CW_WatchDog_Clear 0xA005
// Bit set //
.DEFINE CB_WDPS0 0
.DEFINE CB_WDPS1 1
.DEFINE CB_WDPS2 2
.DEFINE CB_WDCHK0 3
.DEFINE CB_WDCHK1 4
.DEFINE CB_WDCHK2 5
.DEFINE CB_WDCHK3 6
.DEFINE CB_WDCHK4 7
.DEFINE CB_WDRS 14
.DEFINE CB_WDEN 15
// P_Wakeup_Ctrl register //
// word set //
.DEFINE CW_CMTWE_Enable (0x0001<<4)
.DEFINE CW_PDC0WE_Enable (0x0001<<5)
.DEFINE CW_PDC1WE_Enable (0x0001<<6)
.DEFINE CW_TPM2WE_Enable (0x0001<<7)
.DEFINE CW_EXT0WE_Enable (0x0001<<11)
.DEFINE CW_EXT1WE_Enable (0x0001<<12)
.DEFINE CW_SPIWE_Enable (0x0001<<13)
.DEFINE CW_UARTWE_Enable (0x0001<<14)
.DEFINE CW_KEYWE_Enable (0x0001<<15)
// Bit set //
.DEFINE CB_CMTWE_Enable 4
.DEFINE CB_PDC0WE_Enable 5
.DEFINE CB_PDC1WE_Enable 6
.DEFINE CB_TPM2WE_Enable 7
.DEFINE CB_EXT0WE_Enable 11
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