// word set //
.DEFINE CW_TMR1_IOAMOD_Output_00		0x0000
.DEFINE CW_TMR1_IOAMOD_Output_01		0x0001
.DEFINE CW_TMR1_IOAMOD_Output_10		0x0002
.DEFINE CW_TMR1_IOAMOD_Output_11		0x0003
.DEFINE CW_TMR1_IOAMOD_Output_Hold		0x0004
.DEFINE CW_TMR1_IOAMOD_Capture_Rising	0x0008	
.DEFINE CW_TMR1_IOAMOD_Capture_Falling	0x0009	
.DEFINE CW_TMR1_IOAMOD_Capture_Both		0x000A	
.DEFINE CW_TMR1_IOAMOD_Capture_PDR		0x000C	

.DEFINE CW_TMR1_IOBMOD_Output_00		(0x0000 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_01		(0x0001 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_10		(0x0002 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_11		(0x0003 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_Hold		(0x0004 << 4)
.DEFINE CW_TMR1_IOBMOD_Capture_Rising	(0x0008 << 4)	
.DEFINE CW_TMR1_IOBMOD_Capture_Falling	(0x0009 << 4)	
.DEFINE CW_TMR1_IOBMOD_Capture_Both		(0x000A << 4)	
.DEFINE CW_TMR1_IOBMOD_Capture_PDR		(0x000C << 4)	

.DEFINE CW_TMR1_IOCMOD_Output_00		(0x0000 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_01		(0x0001 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_10		(0x0002 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_11		(0x0003 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_Hold		(0x0004 << 8)
.DEFINE CW_TMR1_IOCMOD_Capture_Rising	(0x0008 << 8)	
.DEFINE CW_TMR1_IOCMOD_Capture_Falling	(0x0009 << 8)	
.DEFINE CW_TMR1_IOCMOD_Capture_Both		(0x000A << 8)	
.DEFINE CW_TMR1_IOCMOD_Capture_PDR		(0x000C << 8)	

// Bit set //
.DEFINE CB_TMR1_IOAMOD0					0
.DEFINE CB_TMR1_IOAMOD1					1
.DEFINE CB_TMR1_IOAMOD2					2
.DEFINE CB_TMR1_IOAMOD3					3
.DEFINE CB_TMR1_IOBMOD0					4
.DEFINE CB_TMR1_IOBMOD1					5
.DEFINE CB_TMR1_IOBMOD2					6
.DEFINE CB_TMR1_IOBMOD3					7
.DEFINE CB_TMR1_IOCMOD0					8
.DEFINE CB_TMR1_IOCMOD1					9
.DEFINE CB_TMR1_IOCMOD2					10
.DEFINE CB_TMR1_IOCMOD3					11

// P_TMR2_IOCtrl register //
// word set //
.DEFINE CW_TMR2_IOAMOD_Output_00		0x0000
.DEFINE CW_TMR2_IOAMOD_Output_01		0x0001
.DEFINE CW_TMR2_IOAMOD_Output_10		0x0002
.DEFINE CW_TMR2_IOAMOD_Output_11		0x0003
.DEFINE CW_TMR2_IOAMOD_Output_Hold		0x0004
.DEFINE CW_TMR2_IOAMOD_Capture_Rising	0x0008	
.DEFINE CW_TMR2_IOAMOD_Capture_Falling	0x0009	
.DEFINE CW_TMR2_IOAMOD_Capture_Both		0x000A	

.DEFINE CW_TMR2_IOBMOD_Output_00		(0x0000 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_01		(0x0001 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_10		(0x0002 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_11		(0x0003 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_Hold		(0x0004 << 4)
.DEFINE CW_TMR2_IOBMOD_Capture_Rising	(0x0008 << 4)	
.DEFINE CW_TMR2_IOBMOD_Capture_Falling	(0x0009 << 4)	
.DEFINE CW_TMR2_IOBMOD_Capture_Both		(0x000A << 4)	

// Bit set //
.DEFINE CB_TMR2_IOAMOD0					0
.DEFINE CB_TMR2_IOAMOD1					1
.DEFINE CB_TMR2_IOAMOD2					2
.DEFINE CB_TMR2_IOAMOD3					3
.DEFINE CB_TMR2_IOBMOD0					4
.DEFINE CB_TMR2_IOBMOD1					5
.DEFINE CB_TMR2_IOBMOD2					6
.DEFINE CB_TMR2_IOBMOD3					7

// P_TMR4_IOCtrl register //
// word set //
.DEFINE CW_TMR4_IOAMOD_Output_00		0x0000
.DEFINE CW_TMR4_IOAMOD_Output_01		0x0001
.DEFINE CW_TMR4_IOAMOD_Output_10		0x0002
.DEFINE CW_TMR4_IOAMOD_Output_11		0x0003
.DEFINE CW_TMR4_IOAMOD_Output_Hold		0x0004

.DEFINE CW_TMR4_IOBMOD_Output_00		(0x0000 << 4)
.DEFINE CW_TMR4_IOBMOD_Output_01		(0x0001 << 4)
.DEFINE CW_TMR4_IOBMOD_Output_10		(0x0002 << 4)
.DEFINE CW_TMR4_IOBMOD_Output_11		(0x0003 << 4)
.DEFINE CW_TMR4_IOBMOD_Output_Hold		(0x0004 << 4)

.DEFINE CW_TMR4_IOCMOD_Output_00		(0x0000 << 8)
.DEFINE CW_TMR4_IOCMOD_Output_01		(0x0001 << 8)
.DEFINE CW_TMR4_IOCMOD_Output_10		(0x0002 << 8)
.DEFINE CW_TMR4_IOCMOD_Output_11		(0x0003 << 8)
.DEFINE CW_TMR4_IOCMOD_Output_Hold		(0x0004 << 8)

// Bit set //
.DEFINE CB_TMR4_IOAMOD0					0
.DEFINE CB_TMR4_IOAMOD1					1
.DEFINE CB_TMR4_IOAMOD2					2
.DEFINE CB_TMR4_IOAMOD3					3
.DEFINE CB_TMR4_IOBMOD0					4
.DEFINE CB_TMR4_IOBMOD1					5
.DEFINE CB_TMR4_IOBMOD2					6
.DEFINE CB_TMR4_IOBMOD3					7
.DEFINE CB_TMR4_IOCMOD0					8
.DEFINE CB_TMR4_IOCMOD1					9
.DEFINE CB_TMR4_IOCMOD2					10
.DEFINE CB_TMR4_IOCMOD3					11

// P_TMR0_INT register //
// word set //
.DEFINE CW_TMR0_TGAIE_Enable			0x0001	
.DEFINE CW_TMR0_TGBIE_Enable			(0x0001 << 1)	
.DEFINE CW_TMR0_TGCIE_Enable			(0x0001 << 2)	
.DEFINE CW_TMR0_TPRIE_Enable			(0x0001 << 4)	
.DEFINE CW_TMR0_TCVIE_Enable			(0x0001 << 5)	
.DEFINE CW_TMR0_TCUIE_Enable			(0x0001 << 6)	
.DEFINE CW_TMR0_TADSE_Enable			(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR0_TGAIE					0	
.DEFINE CB_TMR0_TGBIE					1
.DEFINE CB_TMR0_TGCIE					2	
.DEFINE CB_TMR0_TPRIE					4	
.DEFINE CB_TMR0_TCVIE					5	
.DEFINE CB_TMR0_TCUIE					6	
.DEFINE CB_TMR0_TADSE					7	

// P_TMR1_INT register //
// word set //
.DEFINE CW_TMR1_TGAIE_Enable			0x0001	
.DEFINE CW_TMR1_TGBIE_Enable			(0x0001 << 1)	
.DEFINE CW_TMR1_TGCIE_Enable			(0x0001 << 2)	
.DEFINE CW_TMR1_TPRIE_Enable			(0x0001 << 4)	
.DEFINE CW_TMR1_TCVIE_Enable			(0x0001 << 5)	
.DEFINE CW_TMR1_TCUIE_Enable			(0x0001 << 6)	
.DEFINE CW_TMR1_TADSE_Enable			(0x0001 << 7)	
.DEFINE CW_TMR1_PDCIE_Enable			(0x0001 << 8)	

// Bit set //
.DEFINE CB_TMR1_TGAIE					0	
.DEFINE CB_TMR1_TGBIE					1	
.DEFINE CB_TMR1_TGCIE					2
.DEFINE CB_TMR1_TPRIE					4
.DEFINE CB_TMR1_TCVIE					5	
.DEFINE CB_TMR1_TCUIE					6	
.DEFINE CB_TMR1_TADSE					7	
.DEFINE CB_TMR1_PDCIE					8

// P_TMR2_INT register //
// word set //
.DEFINE CW_TMR2_TGAIE_Enable			0x0001	
.DEFINE CW_TMR2_TGBIE_Enable			(0x0001 << 1)	
.DEFINE CW_TMR2_TPRIE_Enable			(0x0001 << 4)	
.DEFINE CW_TMR2_TADSE_Enable			(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR2_TGAIE					0	
.DEFINE CB_TMR2_TGBIE					1	
.DEFINE CB_TMR2_TPRIE					4	
.DEFINE CB_TMR2_TADSE					7

// P_TMR4_INT register //
// word set //
.DEFINE CW_TMR4_TGDIE_Enable			(0x0001 << 3)	
.DEFINE CW_TMR4_TPRIE_Enable			(0x0001 << 4)	
.DEFINE CW_TMR4_TADSE_Enable			(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR4_TGDIE					3	
.DEFINE CB_TMR4_TPRIE					4	
.DEFINE CB_TMR4_TADSE					7

// P_TMR0_Status register //
// word set //
.DEFINE CW_TMR0_TGAIF_Enable			0x0001	
.DEFINE CW_TMR0_TGBIF_Enable			(0x0001 << 1)	
.DEFINE CW_TMR0_TGCIF_Enable			(0x0001 << 2)	
.DEFINE CW_TMR0_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR0_TCVIF_Enable			(0x0001 << 5)	
.DEFINE CW_TMR0_TCUIF_Enable			(0x0001 << 6)	
.DEFINE CW_TMR0_TCDF_Enable				(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR0_TGAIF					0	
.DEFINE CB_TMR0_TGBIF					1
.DEFINE CB_TMR0_TGCIF					2	
.DEFINE CB_TMR0_TPRIF					3
.DEFINE CB_TMR0_TCVIF					4
.DEFINE CB_TMR0_TCUIF					6	
.DEFINE CB_TMR0_TCDF					7	

// P_TMR1_Status register //
// word set //
.DEFINE CW_TMR1_TGAIF_Enable			0x0001	
.DEFINE CW_TMR1_TGBIF_Enable			(0x0001 << 1)	
.DEFINE CW_TMR1_TGCIF_Enable			(0x0001 << 2)	
.DEFINE CW_TMR1_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR1_TCVIF_Enable			(0x0001 << 5)	
.DEFINE CW_TMR1_TCUIF_Enable			(0x0001 << 6)	
.DEFINE CW_TMR1_TCDF_Enable				(0x0001 << 7)	
.DEFINE CW_TMR1_PDCIF_Enable			(0x0001 << 8)	

// Bit set //
.DEFINE CB_TMR1_TGAIF					0	
.DEFINE CB_TMR1_TGBIF					1	
.DEFINE CB_TMR1_TGCIF					2
.DEFINE CB_TMR1_TPRIF					3	
.DEFINE CB_TMR1_TCVIF					4	
.DEFINE CB_TMR1_TCUIF					5
.DEFINE CB_TMR1_TCDF					6	
.DEFINE CB_TMR1_PDCIF					7

// P_TMR2_Status register //
// word set //
.DEFINE CW_TMR2_TGAIF_Enable			0x0001	
.DEFINE CW_TMR2_TGBIF_Enable			(0x0001 << 1)	
.DEFINE CW_TMR2_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR2_TCDF_Enable				(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR2_TGAIF_Enable			0	
.DEFINE CB_TMR2_TGBIF_Enable			1
.DEFINE CB_TMR2_TPRIF_Enable			4
.DEFINE CB_TMR2_TCDF_Enable				7

// P_TMR4_Status register //
// word set //
.DEFINE CW_TMR4_TGDIF_Enable			(0x0001 << 3)	
.DEFINE CW_TMR4_TPRIF_Enable			(0x0001 << 4)	
.DEFINE CW_TMR4_TCDF_Enable				(0x0001 << 7)	

// Bit set //
.DEFINE CB_TMR4_TGDIF_Enable			3
.DEFINE CB_TMR4_TPRIF_Enable			4
.DEFINE CB_TMR4_TCDF_Enable				7

// P_TMR_Start register //
// word set //
.DEFINE CW_TMR_TMR0ST_Start				0x0001	
.DEFINE CW_TMR_TMR1ST_Start				(0x0001 << 1)	
.DEFINE CW_TMR_TMR2ST_Start				(0x0001 << 2)	
.DEFINE CW_TMR_TMR4ST_Start				(0x0001 << 4)	

// Bit set //
.DEFINE CB_TMR_TMR0ST_Start				0	
.DEFINE CB_TMR_TMR1ST_Start				1	
.DEFINE CB_TMR_TMR2ST_Start				2
.DEFINE CB_TMR_TMR4ST_Start				4

// P_TMR_Output register //
// word set //
.DEFINE CW_TMR_TMR4AOE_Enable			(0x0001 << 8)
.DEFINE CW_TMR_TMR4BOE_Enable			(0x0001 << 9)
.DEFINE CW_TMR_TMR4COE_Enable			(0x0001 << 10)
.DEFINE CW_TMR_TMR4DOE_Enable			(0x0001 << 11)
.DEFINE CW_TMR_TMR4EOE_Enable			(0x0001 << 12)
.DEFINE CW_TMR_TMR4FOE_Enable			(0x0001 << 13)

// Bit set //
.DEFINE CB_TMR_TMR4AOE_Enable			8
.DEFINE CB_TMR_TMR4BOE_Enable			9
.DEFINE CB_TMR_TMR4COE_Enable			10
.DEFINE CB_TMR_TMR4DOE_Enable			11
.DEFINE CB_TMR_TMR4EOE_Enable			12
.DEFINE CB_TMR_TMR4FOE_Enable			13

// P_TMR4_OutputCtrl register //
// word set //
.DEFINE CW_TMR4_UOC_Out1				0x0000	
.DEFINE CW_TMR4_UOC_Out2				0x0001
.DEFINE CW_TMR4_UOC_Out3				0x0002
.DEFINE CW_TMR4_UOC_Out4				0x0003

.DEFINE CW_TMR4_VOC_Out1				(0x0000 << 2)	
.DEFINE CW_TMR4_VOC_Out2				(0x0001 << 2)
.DEFINE CW_TMR4_VOC_Out3				(0x0002 << 2)
.DEFINE CW_TMR4_VOC_Out4				(0x0003 << 2)

.DEFINE CW_TMR4_WOC_Out1				(0x0000 << 4)	
.DEFINE CW_TMR4_WOC_Out2				(0x0001 << 4)
.DEFINE CW_TMR4_WOC_Out3				(0x0002 << 4)
.DEFINE CW_TMR4_WOC_Out4				(0x0003 << 4)

.DEFINE CW_TMR4_SYNC_NoSync				(0x0000 << 6)	
.DEFINE CW_TMR4_SYNC_PDR				(0x0001 << 6)	
.DEFINE CW_TMR4_SYNC_TGB				(0x0002 << 6)	
.DEFINE CW_TMR4_SYNC_TGC				(0x0003 << 6)	

.DEFINE CW_TMR4_UPWM_Out_HL				(0x0000 << 8)	
.DEFINE CW_TMR4_UPWM_Out_PWM			(0x0001 << 8)	
.DEFINE CW_TMR4_VPWM_Out_HL				(0x0000 << 9)	
.DEFINE CW_TMR4_VPWM_Out_PWM			(0x0001 << 9)	
.DEFINE CW_TMR4_WPWM_Out_HL				(0x0000 << 10)
.DEFINE CW_TMR4_WPWM_Out_PWM			(0x0001 << 10)

.DEFINE CW_TMR4_POLP_Active_Low			(0x0000 << 14)
.DEFINE CW_TMR4_POLP_Active_High		(0x0001 << 14)

.DEFINE CW_TMR4_DUTYMODE_UCom			(0x0000 << 15)
.DEFINE CW_TMR4_DUTYMODE_Independent	(0x0001 << 15)

// Bit set //
.DEFINE CB_TMR4_UOC0					0	
.DEFINE CB_TMR4_UOC1					1
.DEFINE CB_TMR4_VOC0					2	
.DEFINE CB_TMR4_VOC1					3
.DEFINE CB_TMR4_WOC0					4	
.DEFINE CB_TMR4_WOC1					5
.DEFINE CB_TMR4_SYNC0					6	
.DEFINE CB_TMR4_SYNC1					7		
.DEFINE CB_TMR4_UPWM					8		
.DEFINE CB_TMR4_VPWM					9	
.DEFINE CB_TMR4_WPWM					10
.DEFINE CB_TMR4_POLP_Active				14
.DEFINE CB_TMR4_DUTYMODE				15

// P_POS1_DectCtrl register //							//Timer 1 Position Detection Control Register
// word set //
.DEFINE CW_TMR1_PDCR_PDEN				(0x0001 << 7)

.DEFINE CW_TMR1_PDCR_SPLMOD_Mode1		(0x0000 << 12)
.DEFINE CW_TMR1_PDCR_SPLMOD_Mode2		(0x0001 << 12)
.DEFINE CW_TMR1_PDCR_SPLMOD_Mode3		(0x0002 << 12)

.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv4		(0x0000 << 14)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv8		(0x0001 << 14)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv16		(0x0002 << 14)
.DEFINE CW_TMR1_PDCR_SPLCK_FCKdiv32		(0x0003 << 14)

// Bit set //
.DEFINE CB_TMR1_PDCR_PDEN				7
.DEFINE CB_TMR1_PDCR_SPLMOD0			12
.DEFINE CB_TMR1_PDCR_SPLMOD1			13
.DEFINE CB_TMR1_PDCR_SPLCK0				14
.DEFINE CB_TMR1_PDCR_SPLCK1				15

// P_POS1_DectData register //							//Timer 1 Position Detection Register
// word set //
.DEFINE CW_TMR1_PDR_TIO1A				0x0001
.DEFINE CW_TMR1_PDR_TIO1B				(0x0001 << 1)
.DEFINE CW_TMR1_PDR_TIO1C				(0x0001 << 2)

// Bit set //
.DEFINE CB_TMR1_PDR_TIO1A				0
.DEFINE CB_TMR1_PDR_TIO1B				1
.DEFINE CB_TMR1_PDR_TIO1C				2

// P_TMR4_DeadTime register //							//Timer 4 Dead Time Control Register
// word set //
.DEFINE CW_TMR4_DTCR_DTUE				(0x0001 << 12)
.DEFINE CW_TMR4_DTCR_DTVE				(0x0001 << 13)
.DEFINE CW_TMR4_DTCR_DTWE				(0x0001 << 14)

// Bit set //
.DEFINE CB_TMR4_DTCR_DTUE				12
.DEFINE CB_TMR4_DTCR_DTVE				13
.DEFINE CB_TMR4_DTCR_DTWE				14

// P_TPWM_Write register //								//Timer /PWM Module Write Enable Control Register
// word set //
.DEFINE CW_TWCR_TMR4WE					(0x0001 << 1)

// Bit set //
.DEFINE CB_TWCR_TMR4WE					1

// P_Fault2_Ctrl register //							//Timer 4 Fault Input Control Register
// vord set //
.DEFINE CW_TMR4_FCR_FTPINIF				(0x0001 << 5)
.DEFINE CW_TMR4_FCR_FTPINIE				(0x0001 << 6)
.DEFINE CW_TMR4_FCR_FTPINE				(0x0001 << 7)
.DEFINE CW_TMR4_FCR_OSF					(0x0001 << 12)

.DEFINE CW_TMR4_FCR_OCLS_Low			(0x0000 << 13)