?? spmc75f2313a.inc
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.DEFINE CW_TMR4_FCR_OCLS_High (0x0001 << 13)
.DEFINE CW_TMR4_FCR_OCIE (0x0001 << 14)
.DEFINE CW_TMR4_FCR_OCE (0x0001 << 15)
// Bit set //
.DEFINE CB_TMR4_FCR_FTPINIF 5
.DEFINE CB_TMR4_FCR_FTPINIE 6
.DEFINE CB_TMR4_FCR_FTPINE 7
.DEFINE CB_TMR4_FCR_OSF 12
.DEFINE CB_TMR4_FCR_OCLS 13
.DEFINE CB_TMR4_FCR_OCIE 14
.DEFINE CB_TMR4_FCR_OCE 15
// P_OL2_Ctrl register // //Timer 4 Overload Protecttion Control/Status Register
// word set //
.DEFINE CW_TMR4_OPR_RTOL (0x0001 << 8)
.DEFINE CW_TMR4_OPR_RTPWM_Enable (0x0001 << 9)
.DEFINE CW_TMR4_OPR_RTTMB_Enable (0x0001 << 10)
.DEFINE CW_TMR4_OPR_OLST_UP (0x0001 << 11)
.DEFINE CW_TMR4_OPR_OLMD_NoDis (0x0000 << 12)
.DEFINE CW_TMR4_OPR_OLMD_AllDis (0x0001 << 12)
.DEFINE CW_TMR4_OPR_OLMD_PWMDis (0x0002 << 12)
.DEFINE CW_TMR4_OPR_OLMD_Dis (0x0003 << 12)
.DEFINE CW_TMR4_OPR_CNTSP (0x0001 << 14)
.DEFINE CW_TMR4_OPR_OLEN (0x0001 << 15)
// Bit set //
.DEFINE CB_TMR4_OPR_RTOL 8
.DEFINE CB_TMR4_OPR_RTPWM_Enable 9
.DEFINE CB_TMR4_OPR_RTTMB_Enable 10
.DEFINE CB_TMR4_OPR_OLST_UP 11
.DEFINE CB_TMR4_OPR_OLMD0 12
.DEFINE CB_TMR4_OPR_OLMD1 13
.DEFINE CB_TMR4_OPR_CNTSP 14
.DEFINE CB_TMR4_OPR_OLEN 15
// P_TMR_LDOK register */ //Timer Load Ok Control Register
// word set */
.DEFINE CW_TMR_LDOK1 0x00AA //P_TMR4_TGRA-C ok to load bit
//=================================//
// C. 10-bit A/D Converter register//
//=================================//
// P_ADC_Setup register //
// word set //
.DEFINE CW_ADC_ASPEN (0x0001 << 7)
.DEFINE CW_ADC_ADCEXTRG_Disable (0x0000 << 8)
.DEFINE CW_ADC_ADCEXTRG_Enable (0x0001 << 8)
.DEFINE CW_ADC_ADCFS_CPUCLKdiv8 (0x0000 << 9)
.DEFINE CW_ADC_ADCFS_CPUCLKdiv16 (0x0001 << 9)
.DEFINE CW_ADC_ADCFS_CPUCLKdiv32 (0x0002 << 9)
.DEFINE CW_ADC_ADCFS_CPUCLKdiv64 (0x0003 << 9)
.DEFINE CW_ADC_VRXEN_Internal (0x0000 << 12)
.DEFINE CW_ADC_VRXEN_External (0x0001 << 12)
.DEFINE CW_ADC_ADCEN (0x0001 << 14)
.DEFINE CW_ADC_ADCCS_Select (0x0001 << 15)
.DEFINE CW_ADC_ADCCS_UnSelect (0x0000 << 15)
// Bit set //
.DEFINE CB_ADC_ASPEN 7
.DEFINE CB_ADC_ADCEXTRG 8
.DEFINE CB_ADC_ADCFS0 9
.DEFINE CB_ADC_ADCFS1 10
.DEFINE CB_ADC_VRXEN 12
.DEFINE CB_ADC_ADCEN 14
.DEFINE CB_ADC_ADCCS 15
// P_ADC_Ctrl register //
// word set //
.DEFINE CW_ADC_ADCCHS_Ch2 0x0002
.DEFINE CW_ADC_ADCCHS_Ch3 0x0003
.DEFINE CW_ADC_ADCCHS_Ch4 0x0004
.DEFINE CW_ADC_ADCCHS_Ch5 0x0005
.DEFINE CW_ADC_ADCCHS_Ch6 0x0006
.DEFINE CW_ADC_ADCCHS_Ch7 0x0007
.DEFINE CW_ADC_ADCSTR (0x0001 << 6)
.DEFINE CW_ADC_ADCRDY (0x0001 << 7)
.DEFINE CW_ADC_ADCIE (0x0001 << 14)
.DEFINE CW_ADC_ADCIF (0x0001 << 15)
// Bit set //
.DEFINE CB_ADC_ADCCHS0 0
.DEFINE CB_ADC_ADCCHS1 1
.DEFINE CB_ADC_ADCCHS2 2
.DEFINE CB_ADC_ADCSTR 6
.DEFINE CB_ADC_ADCRDY 7
.DEFINE CB_ADC_ADCIE 14
.DEFINE CB_ADC_ADCIF 15
// P_ADC_Channel register //
// word set //
.DEFINE CW_ADC_ADCCH2_Enable (0x0001 << 2)
.DEFINE CW_ADC_ADCCH3_Enable (0x0001 << 3)
.DEFINE CW_ADC_ADCCH4_Enable (0x0001 << 4)
.DEFINE CW_ADC_ADCCH5_Enable (0x0001 << 5)
.DEFINE CW_ADC_ADCCH6_Enable (0x0001 << 6)
.DEFINE CW_ADC_ADCCH7_Enable (0x0001 << 7)
// Bit set //
.DEFINE CB_ADC_ADCCH2_Enable 2
.DEFINE CB_ADC_ADCCH3_Enable 3
.DEFINE CB_ADC_ADCCH4_Enable 4
.DEFINE CB_ADC_ADCCH5_Enable 5
.DEFINE CB_ADC_ADCCH6_Enable 6
.DEFINE CB_ADC_ADCCH7_Enable 7
//=================================//
// D. SPI register //
//=================================//
// P_SPI_Ctrl register //
// word set //
.DEFINE CW_SPI_SPIFS_CPUCLKdiv4 0x0000
.DEFINE CW_SPI_SPIFS_CPUCLKdiv8 0x0001
.DEFINE CW_SPI_SPIFS_CPUCLKdiv16 0x0002
.DEFINE CW_SPI_SPIFS_CPUCLKdiv32 0x0003
.DEFINE CW_SPI_SPIFS_CPUCLKdiv64 0x0004
.DEFINE CW_SPI_SPIFS_CPUCLKdiv128 0x0005
.DEFINE CW_SPI_SPISMPS_Middle (0x0000 << 3)
.DEFINE CW_SPI_SPISMPS_End (0x0001 << 3)
.DEFINE CW_SPI_SPIPOL (0x0001 << 4)
.DEFINE CW_SPI_SPIPHA (0x0001 << 5)
.DEFINE CW_SPI_SPIMS_Master (0x0000 << 8)
.DEFINE CW_SPI_SPIMS_Slave (0x0001 << 8)
.DEFINE CW_SPI_SPISPCLK_NO (0x0000 << 9)
.DEFINE CW_SPI_SPISPCLK_FCK (0x0001 << 9)
.DEFINE CW_SPI_SPISPCLK_FCKdiv2 (0x0002 << 9)
.DEFINE CW_SPI_SPISPCLK_FCKdiv4 (0x0003 << 9)
.DEFINE CW_SPI_SPIRST (0x0001 << 11)
.DEFINE CW_SPI_SPIE (0x0001 << 15)
// Bit set //
.DEFINE CB_SPI_SPIFS0 0
.DEFINE CB_SPI_SPIFS1 1
.DEFINE CB_SPI_SPIFS2 2
.DEFINE CB_SPI_SPISMPS 3
.DEFINE CB_SPI_SPIPOL 4
.DEFINE CB_SPI_SPIPHA 5
.DEFINE CB_SPI_SPIMS 8
.DEFINE CB_SPI_SPISPCLK0 9
.DEFINE CB_SPI_SPISPCLK1 10
.DEFINE CB_SPI_SPIRST 11
.DEFINE CB_SPI_SPIE 15
// P_SPI_TxStatus register //
// word set //
.DEFINE CW_SPI_SPITXBF (0x0001 << 13)
.DEFINE CW_SPI_SPITXIE (0x0001 << 14)
.DEFINE CW_SPI_SPITXIF (0x0001 << 15)
// Bit set //
.DEFINE CB_SPI_SPITXBF 13
.DEFINE CB_SPI_SPITXIE 14
.DEFINE CB_SPI_SPITXIF 15
// P_SPI_RxStatus register //
// word set //
.DEFINE CW_SPI_FERR (0x0001 << 10)
.DEFINE CW_SPI_SPIRXIE (0x0001 << 14)
.DEFINE CW_SPI_SPIRXIF (0x0001 << 15)
// Bit set //
.DEFINE CB_SPI_FERR 10
.DEFINE CB_SPI_SPIRXIE 14
.DEFINE CB_SPI_SPIRXIF 15
// P_UART_Data register //
// word set //
.DEFINE CW_UARTData_FE (0x0001 << 8)
.DEFINE CW_UARTData_PE (0x0001 << 9)
.DEFINE CW_UARTData_OE (0x0001 << 11)
// Bit set //
.DEFINE CB_UARTData_FE 8
.DEFINE CB_UARTData_PE 9
.DEFINE CB_UARTData_OE 11
// P_UART_RXStatus register //
// word set //
.DEFINE CW_UARTRx_FE 0x0001
.DEFINE CW_UARTRx_PE (0x0001 << 1)
.DEFINE CW_UARTRx_OE (0x0001 << 3)
.DEFINE CW_UART_Clear_FE 0x0001
.DEFINE CW_UART_Clear_PE (0x0001 << 1)
.DEFINE CW_UART_Clear_OE (0x0001 << 3)
// Bit set //
.DEFINE CB_UARTRx_FE 0
.DEFINE CB_UARTRx_PE 1
.DEFINE CB_UARTRx_OE 2
// P_UART_Ctrl register //
// word set //
.DEFINE CW_UART_PEN (0x0001 << 1)
.DEFINE CW_UART_PSEL_Odd (0x0000 << 2)
.DEFINE CW_UART_PSEL_Even (0x0001 << 2)
.DEFINE CW_UART_SBSEL_1Stop (0x0000 << 3)
.DEFINE CW_UART_SBSEL_2Stop (0x0001 << 3)
.DEFINE CW_UART_RXCHSEL_No1 (0x0001<<9)
.DEFINE CW_UART_TXCHSEL_No1 (0x0001<<10)
.DEFINE CW_UART_Reset (0x0001 << 11)
.DEFINE CW_UART_TXEN (0x0001 << 12)
.DEFINE CW_UART_RXEN (0x0001 << 13)
.DEFINE CW_UART_TXIE (0x0001 << 14)
.DEFINE CW_UART_RXIE (0x0001 << 15)
// Bit set //
.DEFINE CB_UART_PEN 1
.DEFINE CB_UART_PSEL 2
.DEFINE CB_UART_SBSEL 3
.DEFINE CB_UART_RXCHSEL 9
.DEFINE CB_UART_TXCHSEL 10
.DEFINE CB_UART_Reset 11
.DEFINE CB_UART_TXEN 12
.DEFINE CB_UART_RXEN 13
.DEFINE CB_UART_TXIE 14
.DEFINE CB_UART_RXIE 15
// P_UART_BaudRate register //
// word set //
.DEFINE CW_UARTBUD_1200 0xFB1E //1200 bps Set
.DEFINE CW_UARTBUD_2400 0xFD8F //2400 bps Set
.DEFINE CW_UARTBUD_4800 0xFEC8 //4800 bps Set
.DEFINE CW_UARTBUDR_9600 0xFF64 //9600 bps Set
.DEFINE CW_UARTBUD_19200 0xFFB2 //19200 bps Set
.DEFINE CW_UARTBUD_57600 0xFFE6 //57600 bps Set
.DEFINE CW_UARTBUD_115200 0xFFF3 //115200 bps Set
// P_UART_Status register //
// word set //
.DEFINE CW_UART_Ready (0x0000 << 3)
.DEFINE CW_UART_BY (0x0001 << 3)
.DEFINE CW_UART_RXBF (0x0001 << 6)
.DEFINE CW_UART_TXIF (0x0001 << 14)
.DEFINE CW_UART_RXIF (0x0001 << 15)
// Bit set //
.DEFINE CB_UART_BY 3
.DEFINE CB_UART_RXBF 6
.DEFINE CB_UART_TXIF 14
.DEFINE CB_UART_RXIF 15
// P_INT_Status register //
// word set //
.DEFINE CW_INT_FTIF 0x0001
.DEFINE CW_INT_OSCSF (0x0001 << 1)
.DEFINE CW_INT_CMTIF (0x0001 << 4)
.DEFINE CW_INT_PDC1IF (0x0001 << 6)
.DEFINE CW_INT_TPM2IF (0x0001 << 7)
.DEFINE CW_INT_MCP4IF (0x0001 << 9)
.DEFINE CW_INT_ADCIF (0x0001 << 10)
.DEFINE CW_INT_SPIIF (0x0001 << 13)
.DEFINE CW_INT_UARTIF (0x0001 << 14)
.DEFINE CW_INT_KEYIF (0x0001 << 15)
// Bit set //
.DEFINE CB_INT_FTIF 0
.DEFINE CB_INT_OSCSF 1
.DEFINE CB_INT_CMTIF 4
.DEFINE CB_INT_PDC1IF 6
.DEFINE CB_INT_TPM2IF 7
.DEFINE CB_INT_MCP4IF 9
.DEFINE CB_INT_ADCIF 10
.DEFINE CB_INT_SPIIF 13
.DEFINE CB_INT_UARTIF 14
.DEFINE CB_INT_KEYIF 15
// P_INT_Priority register //
// word set //
.DEFINE CW_INT_FTIP 0x0001
.DEFINE CW_INT_OSCIP (0x0001 << 1)
.DEFINE CW_INT_CMTIP (0x0001 << 4)
.DEFINE CW_INT_PDC1IP (0x0001 << 6)
.DEFINE CW_INT_TPM2IP (0x0001 << 7)
.DEFINE CW_INT_MCP4IP (0x0001 << 9)
.DEFINE CW_INT_ADCIP (0x0001 << 10)
.DEFINE CW_INT_SPIIP (0x0001 << 13)
.DEFINE CW_INT_UARTIP (0x0001 << 14)
.DEFINE CW_INT_KEYIP (0x0001 << 15)
// Bit set //
.DEFINE CB_INT_FTIP 0
.DEFINE CB_INT_OSCIP 1
.DEFINE CB_INT_CMTIP 4
.DEFINE CB_INT_PDC1IP 6
.DEFINE CB_INT_TPM2IP 7
.DEFINE CB_INT_ADCIP 10
.DEFINE CB_INT_SPIIP 13
.DEFINE CB_INT_UARTIP 14
.DEFINE CB_INT_KEYIP 15
// P_MisINT_Ctrl register //
// word set //
.DEFINE CW_INT_KEYIE (0x0001 << 15)
// Bit set //
.DEFINE CB_INT_KEYIE 15
//=================================//
// H. Compare Match Time Register //
//=================================//
// P_CMT_Start register //
// word set //
.DEFINE CW_CMT0_Start 0x0001
.DEFINE CW_CMT1_Start 0x0002
// Bit set //
.DEFINE CB_CMT0_Start 0
.DEFINE CB_CMT1_Start 1
// P_CMT_Ctrl register //
// word set //
.DEFINE CW_CKA_FCK_1 0x0000 //CKA = FCK / 1
.DEFINE CW_CKA_FCK_2 0x0001 //CKA = FCK / 2
.DEFINE CW_CKA_FCK_4 0x0002 //CKA = FCK / 4
.DEFINE CW_CKA_FCK_8 0x0003 //CKA = FCK / 8
.DEFINE CW_CKA_FCK_16 0x0004 //CKA = FCK / 16
.DEFINE CW_CKA_FCK_64 0x0005 //CKA = FCK / 64
.DEFINE CW_CKA_FCK_256 0x0006 //CKA = FCK / 256
.DEFINE CW_CKA_FCK_1024 0x0007 //CKA = FCK / 1024
.DEFINE CW_CMT0_INT_EN 0x0040 //CMT0 compare match interrupt enable
.DEFINE CW_CLEAR_CM0IF 0x0080
.DEFINE CW_CKB_FCK_1 0x0000 //CKA = FCK / 1
.DEFINE CW_CKB_FCK_2 0x0100 //CKA = FCK / 2
.DEFINE CW_CKB_FCK_4 0x0200 //CKA = FCK / 4
.DEFINE CW_CKB_FCK_8 0x0300 //CKA = FCK / 8
.DEFINE CW_CKB_FCK_16 0x0400 //CKA = FCK / 16
.DEFINE CW_CKB_FCK_64 0x0500 //CKA = FCK / 64
.DEFINE CW_CKB_FCK_256 0x0600 //CKA = FCK / 256
.DEFINE CW_CKB_FCK_1024 0x0700 //CKA = FCK / 1024
.DEFINE CW_CMT1_INT_EN 0x4000 //CMT1 compare match interrupt enable
.DEFINE CW_CLEAR_CM1IF 0x8000
// Bit set //
.DEFINE CB_CKA_FCK0 0
.DEFINE CB_CKA_FCK1 1
.DEFINE CB_CKA_FCK2 2
.DEFINE CB_CMT0_INT_EN 2
.DEFINE CB_CLEAR_CM0IF 3
.DEFINE CB_CKB_FCK0 8
.DEFINE CB_CKB_FCK1 9
.DEFINE CB_CKB_FCK2 10
.DEFINE CB_CMT1_INT_EN 14
.DEFINE CB_CLEAR_CM1IF 15?? 快捷鍵說明
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