?? lpc2300.s
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;/*****************************************************************************/
;/* LPC2300.S: Startup file for Philips LPC2300 device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2006 Keil - An ARM Company. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The LPC2300.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set the startup code initializes the register MEMMAP
; * which overwrites the settings of the CPU configuration pins. The
; * startup and interrupt vectors are remapped from:
; * 0x00000000 default setting (not remapped)
; * 0x40000000 when RAM_MODE is used
; *
; * RAM_MODE: when set the device is configured for code execution
; * from on-chip RAM starting at address 0x40000000.
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000020
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000050
Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
Stack_Top EQU Stack_Mem + Stack_Size
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem SPACE Heap_Size
; System Control Block (SCB) Module Definitions
SCB_BASE EQU 0xE01FC000 ; SCB Base Address
PLLCON_OFS EQU 0x80 ; PLL Control Offset
PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x88 ; PLL Status Offset
PLLFEED_OFS EQU 0x8C ; PLL Feed Offset
CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset
USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset
CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset
SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset
PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset
PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset
; Constants
OSCRANGE EQU (1<<4) ; Oscillator Range Select
OSCEN EQU (1<<5) ; Main oscillator Enable
OSCSTAT EQU (1<<6) ; Main Oscillator Status
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value
PLLSTAT_N EQU (0xFF<<16) ; PLL N Value
PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status
;// <e> Clock Setup
;// <h> System Controls and Status Register (SYS)
;// <o1.4> OSCRANGE: Main Oscillator Range Select
;// <0=> 1 MHz to 20 MHz
;// <1=> 15 MHz to 24 MHz
;// <e1.5> OSCEN: Main Oscillator Enable
;// </e>
;// </h>
;//
;// <h> PLL Clock Source Select Register (CLKSRCSEL)
;// <o2.0..1> CLKSRC: PLL Clock Source Selection
;// <0=> Internal RC oscillator
;// <1=> Main oscillator
;// <1=> RTC oscillator
;// </h>
;//
;// <h> PLL Configuration Register (PLLCFG)
;// <i> PLL_clk = (2* M * PLL_clk_src) / N
;// <o3.0..14> MSEL: PLL Multiplier Selection
;// <1-32768><#-1>
;// <i> M Value
;// <o3.16..23> NSEL: PLL Divider Selection
;// <1-256><#-1>
;// <i> N Value
;// </h>
;//
;// <h> CPU Clock Configuration Register (CCLKCFG)
;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL
;// <1-256><#-1>
;// </h>
;//
;// <h> USB Clock Configuration Register (USBCLKCFG)
;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL
;// <1-16><#-1>
;// </h>
;//
;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 6
;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 6
;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 6
;// </h>
;//
;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Cclk / 8
;// <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
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