/* * This file was generated by optab.pl - do not edit. */#include "common-x86.h"#include "operands-x86.h"#include "optab-x86.h"#include "regs-x86.h"static struct x86OpCode Instructions[] = {  { I_AAA, 0, { 0, 0, 0 }, "\x37", 1, -1, { -1, -1, -1 } },  { I_AAD, 0, { 0, 0, 0 }, "\xD5\x0A", 2, -1, { -1, -1, -1 } },  { I_AAD, 1, { IMMEDIATE|BITS8, 0, 0 }, "\xD5", 1, -1, { -1, -1, -1 } },  { I_AAM, 0, { 0, 0, 0 }, "\xD4\x0A", 2, -1, { -1, -1, -1 } },  { I_AAM, 1, { IMMEDIATE|BITS8, 0, 0 }, "\xD4", 1, -1, { -1, -1, -1 } },  { I_AAS, 0, { 0, 0, 0 }, "\x3F", 1, -1, { -1, -1, -1 } },  { I_ADC, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x14", 1, -1, { R_AL, -1, -1 } },  { I_ADC, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x15", 1, -1, { R_AX, -1, -1 } },  { I_ADC, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x15", 1, -1, { R_EAX, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 2, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 2, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 2, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 2, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 2, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS8, REG8, 0 }, "\x10", 1, REGRM, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS16, REG16, 0 }, "\x11", 1, REGRM, { -1, -1, -1 } },  { I_ADC, 2, { REGMEM|BITS32, REG32, 0 }, "\x11", 1, REGRM, { -1, -1, -1 } },  { I_ADC, 2, { REG8, REGMEM|BITS8, 0 }, "\x12", 1, REGRM, { -1, -1, -1 } },  { I_ADC, 2, { REG16, REGMEM|BITS16, 0 }, "\x13", 1, REGRM, { -1, -1, -1 } },  { I_ADC, 2, { REG32, REGMEM|BITS32, 0 }, "\x13", 1, REGRM, { -1, -1, -1 } },  { I_ADD, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x04", 1, -1, { R_AL, -1, -1 } },  { I_ADD, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x05", 1, -1, { R_AX, -1, -1 } },  { I_ADD, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x05", 1, -1, { R_EAX, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 0, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 0, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 0, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 0, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 0, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS8, REG8, 0 }, "\x00", 1, REGRM, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS16, REG16, 0 }, "\x01", 1, REGRM, { -1, -1, -1 } },  { I_ADD, 2, { REGMEM|BITS32, REG32, 0 }, "\x01", 1, REGRM, { -1, -1, -1 } },  { I_ADD, 2, { REG8, REGMEM|BITS8, 0 }, "\x02", 1, REGRM, { -1, -1, -1 } },  { I_ADD, 2, { REG16, REGMEM|BITS16, 0 }, "\x03", 1, REGRM, { -1, -1, -1 } },  { I_ADD, 2, { REG32, REGMEM|BITS32, 0 }, "\x03", 1, REGRM, { -1, -1, -1 } },  { I_ADDPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x58", 2, REGRM, { -1, -1, -1 } },  { I_AND, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x24", 1, -1, { R_AL, -1, -1 } },  { I_AND, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x25", 1, -1, { R_AX, -1, -1 } },  { I_AND, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x25", 1, -1, { R_EAX, -1, -1 } },  { I_AND, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 4, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 4, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 4, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 4, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 4, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS8, REG8, 0 }, "\x20", 1, REGRM, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS16, REG16, 0 }, "\x21", 1, REGRM, { -1, -1, -1 } },  { I_AND, 2, { REGMEM|BITS32, REG32, 0 }, "\x21", 1, REGRM, { -1, -1, -1 } },  { I_AND, 2, { REG8, REGMEM|BITS8, 0 }, "\x22", 1, REGRM, { -1, -1, -1 } },  { I_AND, 2, { REG16, REGMEM|BITS16, 0 }, "\x23", 1, REGRM, { -1, -1, -1 } },  { I_AND, 2, { REG32, REGMEM|BITS32, 0 }, "\x23", 1, REGRM, { -1, -1, -1 } },  { I_ARPL, 2, { REGMEM|BITS16, REG16, 0 }, "\x63", 1, REGRM, { -1, -1, -1 } },  { I_BOUND, 2, { REG16, MEMORY|BITS16, 0 }, "\x62", 1, REGRM, { -1, -1, -1 } },  { I_BOUND, 2, { REG32, MEMORY|BITS32, 0 }, "\x62", 1, REGRM, { -1, -1, -1 } },  { I_BSF, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xBC", 2, REGRM, { -1, -1, -1 } },  { I_BSF, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xBC", 2, REGRM, { -1, -1, -1 } },  { I_BSR, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\xBD", 2, REGRM, { -1, -1, -1 } },  { I_BSR, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\xBD", 2, REGRM, { -1, -1, -1 } },  { I_BSWAP, 1, { REG32, 0, 0 }, "\x0F\xC8", 2, REGCODE, { -1, -1, -1 } },  { I_BT, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xA3", 2, REGRM, { -1, -1, -1 } },  { I_BT, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xA3", 2, REGRM, { -1, -1, -1 } },  { I_BT, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 4, { -1, -1, -1 } },  { I_BT, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 4, { -1, -1, -1 } },  { I_BTC, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xBB", 2, REGRM, { -1, -1, -1 } },  { I_BTC, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xBB", 2, REGRM, { -1, -1, -1 } },  { I_BTC, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 7, { -1, -1, -1 } },  { I_BTC, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 7, { -1, -1, -1 } },  { I_BTR, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xB3", 2, REGRM, { -1, -1, -1 } },  { I_BTR, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xB3", 2, REGRM, { -1, -1, -1 } },  { I_BTR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 6, { -1, -1, -1 } },  { I_BTR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 6, { -1, -1, -1 } },  { I_BTS, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xAB", 2, REGRM, { -1, -1, -1 } },  { I_BTS, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xAB", 2, REGRM, { -1, -1, -1 } },  { I_BTS, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 5, { -1, -1, -1 } },  { I_BTS, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x0F\xBA", 2, 5, { -1, -1, -1 } },  { I_CALL, 1, { RELATIVE|BITS16|NEAR, 0, 0 }, "\xE8", 1, -1, { -1, -1, -1 } },  { I_CALL, 1, { RELATIVE|BITS32|NEAR, 0, 0 }, "\xE8", 1, -1, { -1, -1, -1 } },  { I_CALL, 1, { REGMEM|BITS16|NEAR, 0, 0 }, "\xFF", 1, 2, { -1, -1, -1 } },  { I_CALL, 1, { REGMEM|BITS32|NEAR, 0, 0 }, "\xFF", 1, 2, { -1, -1, -1 } },  { I_CALL, 1, { SEG16|OFF16|FAR, 0, 0 }, "\x9A", 1, -1, { -1, -1, -1 } },  { I_CALL, 1, { SEG16|OFF32|BITS32|FAR, 0, 0 }, "\x9A", 1, -1, { -1, -1, -1 } },  { I_CALL, 1, { REGMEM|BITS16|FAR, 0, 0 }, "\xFF", 1, 3, { -1, -1, -1 } },  { I_CALL, 1, { REGMEM|BITS32|FAR, 0, 0 }, "\xFF", 1, 3, { -1, -1, -1 } },  { I_CBW, 0, { 0, 0, 0 }, "\x98", 1, -1, { -1, -1, -1 } },  { I_CDQ, 0, { BITS32, 0, 0 }, "\x99", 1, -1, { -1, -1, -1 } },  { I_CLC, 0, { 0, 0, 0 }, "\xF8", 1, -1, { -1, -1, -1 } },  { I_CLD, 0, { 0, 0, 0 }, "\xFC", 1, -1, { -1, -1, -1 } },  { I_CLI, 0, { 0, 0, 0 }, "\xFA", 1, -1, { -1, -1, -1 } },  { I_CLTS, 0, { 0, 0, 0 }, "\x0F\x06", 2, -1, { -1, -1, -1 } },  { I_CMC, 0, { 0, 0, 0 }, "\xF5", 1, -1, { -1, -1, -1 } },  { I_CMOVA, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x47", 2, REGRM, { -1, -1, -1 } },  { I_CMOVA, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x47", 2, REGRM, { -1, -1, -1 } },  { I_CMOVC, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x42", 2, REGRM, { -1, -1, -1 } },  { I_CMOVC, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x42", 2, REGRM, { -1, -1, -1 } },  { I_CMOVE, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x44", 2, REGRM, { -1, -1, -1 } },  { I_CMOVE, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x44", 2, REGRM, { -1, -1, -1 } },  { I_CMOVG, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4F", 2, REGRM, { -1, -1, -1 } },  { I_CMOVG, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4F", 2, REGRM, { -1, -1, -1 } },  { I_CMOVL, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4C", 2, REGRM, { -1, -1, -1 } },  { I_CMOVL, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4C", 2, REGRM, { -1, -1, -1 } },  { I_CMOVLE, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4E", 2, REGRM, { -1, -1, -1 } },  { I_CMOVLE, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4E", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNA, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x46", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNA, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x46", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNC, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x43", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNC, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x43", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNE, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x45", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNE, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x45", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNL, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4D", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNL, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4D", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNO, 2, { REG16, REGMEM|BITS32, 0 }, "\x0F\x41", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNO, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x41", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNP, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x4B", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNP, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4B", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x49", 2, REGRM, { -1, -1, -1 } },  { I_CMOVNS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x49", 2, REGRM, { -1, -1, -1 } },  { I_CMOVO, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x40", 2, REGRM, { -1, -1, -1 } },  { I_CMOVO, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x40", 2, REGRM, { -1, -1, -1 } },  { I_CMOVP, 2, { REG16, REGMEM|BITS32, 0 }, "\x0F\x4A", 2, REGRM, { -1, -1, -1 } },  { I_CMOVP, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x4A", 2, REGRM, { -1, -1, -1 } },  { I_CMOVS, 2, { REG16, REGMEM|BITS16, 0 }, "\x0F\x48", 2, REGRM, { -1, -1, -1 } },  { I_CMOVS, 2, { REG32, REGMEM|BITS32, 0 }, "\x0F\x48", 2, REGRM, { -1, -1, -1 } },  { I_CMP, 2, { REGISTER|BITS8, IMMEDIATE|BITS8, 0 }, "\x3C", 1, -1, { R_AL, -1, -1 } },  { I_CMP, 2, { REGISTER|BITS16, IMMEDIATE|BITS16, 0 }, "\x3D", 1, -1, { R_AX, -1, -1 } },  { I_CMP, 2, { REGISTER|BITS32, IMMEDIATE|BITS32, 0 }, "\x3D", 1, -1, { R_EAX, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 7, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 7, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 7, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 7, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 7, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS8, REG8, 0 }, "\x38", 1, REGRM, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS16, REG16, 0 }, "\x39", 1, REGRM, { -1, -1, -1 } },  { I_CMP, 2, { REGMEM|BITS32, REG32, 0 }, "\x39", 1, REGRM, { -1, -1, -1 } },  { I_CMP, 2, { REG8, REGMEM|BITS8, 0 }, "\x3A", 1, REGRM, { -1, -1, -1 } },  { I_CMP, 2, { REG16, REGMEM|BITS16, 0 }, "\x3B", 1, REGRM, { -1, -1, -1 } },  { I_CMP, 2, { REG32, REGMEM|BITS32, 0 }, "\x3B", 1, REGRM, { -1, -1, -1 } },  { I_CMPSB, 0, { 0, 0, 0 }, "\xA6", 1, -1, { -1, -1, -1 } },  { I_CMPSD, 0, { BITS32, 0, 0 }, "\xA7", 1, -1, { -1, -1, -1 } },  { I_CMPSW, 0, { 0, 0, 0 }, "\xA7", 1, -1, { -1, -1, -1 } },  { I_CMPXCHG, 2, { REGMEM|BITS8, REG8, 0 }, "\x0F\xB0", 2, REGRM, { -1, -1, -1 } },  { I_CMPXCHG, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xB1", 2, REGRM, { -1, -1, -1 } },  { I_CMPXCHG, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xB1", 2, REGRM, { -1, -1, -1 } },  { I_CMPXCHG8B, 1, { MEMORY|BITS64, 0, 0 }, "\x0F\xC7", 2, 1, { -1, -1, -1 } },  { I_CPUID, 0, { 0, 0, 0 }, "\x0F\xA2", 2, -1, { -1, -1, -1 } },  { I_CWD, 0, { 0, 0, 0 }, "\x99", 1, -1, { -1, -1, -1 } },  { I_CWDE, 0, { BITS32, 0, 0 }, "\x98", 1, -1, { -1, -1, -1 } },  { I_DAA, 0, { 0, 0, 0 }, "\x27", 1, -1, { -1, -1, -1 } },  { I_DAS, 0, { 0, 0, 0 }, "\x2F", 1, -1, { -1, -1, -1 } },  { I_DEC, 1, { REGMEM|BITS8, 0, 0 }, "\xFE", 1, 1, { -1, -1, -1 } },  { I_DEC, 1, { REGMEM|BITS16, 0, 0 }, "\xFF", 1, 1, { -1, -1, -1 } },  { I_DEC, 1, { REGMEM|BITS32, 0, 0 }, "\xFF", 1, 1, { -1, -1, -1 } },  { I_DEC, 1, { REG16, 0, 0 }, "\x48", 1, REGCODE, { -1, -1, -1 } },  { I_DEC, 1, { REG32, 0, 0 }, "\x48", 1, REGCODE, { -1, -1, -1 } },  { I_DIV, 1, { REGMEM|BITS8, 0, 0 }, "\xF6", 1, 6, { -1, -1, -1 } },  { I_DIV, 1, { REGMEM|BITS16, 0, 0 }, "\xF7", 1, 6, { -1, -1, -1 } },  { I_DIV, 1, { REGMEM|BITS32, 0, 0 }, "\xF7", 1, 6, { -1, -1, -1 } },  { I_EMMS, 0, { 0, 0, 0 }, "\x0F\x77", 2, -1, { -1, -1, -1 } },  { I_ENTER, 2, { IMMEDIATE|BITS16, IMMEDIATE|BITS8, 0 }, "\xC8", 1, -1, { -1, -1, -1 } },  { I_F2XM1, 0, { 0, 0, 0 }, "\xD9\xF0", 2, -1, { -1, -1, -1 } },  { I_FABS, 0, { 0, 0, 0 }, "\xD9\xE1", 2, -1, { -1, -1, -1 } },  { I_FADD, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 0, { R_ST0, -1, -1 } },  { I_FADD, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 0, { R_ST0, -1, -1 } },  { I_FADD, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xC0", 2, FPUCODE, { R_ST0, -1, -1 } },  { I_FADD, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xC0", 2, FPUCODE, { -1, R_ST0, -1 } },  { I_FADDP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xC0", 2, FPUCODE, { -1, R_ST0, -1 } },  { I_FBLD, 2, { REGISTER, MEMORY|BITS80, 0 }, "\xDF", 1, 4, { R_ST0, -1, -1 } },  { I_FBSTP, 2, { MEMORY|BITS80, REGISTER, 0 }, "\xDF", 1, 6, { -1, R_ST0, -1 } },  { I_FCHS, 1, { REGISTER, 0, 0 }, "\xD9\xE0", 2, -1, { R_ST0, -1, -1 } },  { I_FCLEX, 0, { 0, 0, 0 }, "\x9B\xDB\xE2", 3, -1, { -1, -1, -1 } },  { I_FCMOVB, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xC0", 2, FPUCODE, { R_ST0, -1, -1 } },  { I_FCMOVBE, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xD0", 2, FPUCODE, { R_ST0, -1, -1 } },  { I_FCMOVE, 2, { REGISTER, REG_FPU, 0 }, "\xDA\xC8", 2, FPUCODE, { R_ST0, -1, -1 } },  { I_FCMOVNB, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xC0", 2, FPUCODE, { R_ST0, -1, -1 } },  { I_FCMOVNBE, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xD0", 2, FPUCODE, { R_ST0, -1, -1 } },  { I_FCMOVNE, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xC8", 2, FPUCODE, { R_ST0, -1, -1 } },