return 0;    case 0x050: /* RIS */        return s->int_status;    case 0x054: /* IMC */        return s->int_mask;    case 0x058: /* MISC */        return s->int_status & s->int_mask;    case 0x05c: /* RESC */        return s->resc;    case 0x060: /* RCC */        return s->rcc;    case 0x064: /* PLLCFG */        {            int xtal;            xtal = (s->rcc >> 6) & 0xf;            if (s->board->did0 & (1 << 16)) {                return pllcfg_fury[xtal];            } else {                return pllcfg_sandstorm[xtal];            }        }    case 0x100: /* RCGC0 */        return s->rcgc[0];    case 0x104: /* RCGC1 */        return s->rcgc[1];    case 0x108: /* RCGC2 */        return s->rcgc[2];    case 0x110: /* SCGC0 */        return s->scgc[0];    case 0x114: /* SCGC1 */        return s->scgc[1];    case 0x118: /* SCGC2 */        return s->scgc[2];    case 0x120: /* DCGC0 */        return s->dcgc[0];    case 0x124: /* DCGC1 */        return s->dcgc[1];    case 0x128: /* DCGC2 */        return s->dcgc[2];    case 0x150: /* CLKVCLR */        return s->clkvclr;    case 0x160: /* LDOARST */        return s->ldoarst;    case 0x1e0: /* USER0 */        return s->user0;    case 0x1e4: /* USER1 */        return s->user1;    default:        cpu_abort(cpu_single_env, "ssys_read: Bad offset 0x%x\n", (int)offset);        return 0;    }}static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value){    ssys_state *s = (ssys_state *)opaque;    offset -= s->base;    switch (offset) {    case 0x030: /* PBORCTL */        s->pborctl = value & 0xffff;        break;    case 0x034: /* LDOPCTL */        s->ldopctl = value & 0x1f;        break;    case 0x040: /* SRCR0 */    case 0x044: /* SRCR1 */    case 0x048: /* SRCR2 */        fprintf(stderr, "Peripheral reset not implemented\n");        break;    case 0x054: /* IMC */        s->int_mask = value & 0x7f;        break;    case 0x058: /* MISC */        s->int_status &= ~value;        break;    case 0x05c: /* RESC */        s->resc = value & 0x3f;        break;    case 0x060: /* RCC */        if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {            /* PLL enable.  */            s->int_status |= (1 << 6);        }        s->rcc = value;        system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);        break;    case 0x100: /* RCGC0 */        s->rcgc[0] = value;        break;    case 0x104: /* RCGC1 */        s->rcgc[1] = value;        break;    case 0x108: /* RCGC2 */        s->rcgc[2] = value;        break;    case 0x110: /* SCGC0 */        s->scgc[0] = value;        break;    case 0x114: /* SCGC1 */        s->scgc[1] = value;        break;    case 0x118: /* SCGC2 */        s->scgc[2] = value;        break;    case 0x120: /* DCGC0 */        s->dcgc[0] = value;        break;    case 0x124: /* DCGC1 */        s->dcgc[1] = value;        break;    case 0x128: /* DCGC2 */        s->dcgc[2] = value;        break;    case 0x150: /* CLKVCLR */        s->clkvclr = value;        break;    case 0x160: /* LDOARST */        s->ldoarst = value;        break;    default:        cpu_abort(cpu_single_env, "ssys_write: Bad offset 0x%x\n", (int)offset);    }    ssys_update(s);}static CPUReadMemoryFunc *ssys_readfn[] = {   ssys_read,   ssys_read,   ssys_read};static CPUWriteMemoryFunc *ssys_writefn[] = {   ssys_write,   ssys_write,   ssys_write};static void ssys_reset(void *opaque){    ssys_state *s = (ssys_state *)opaque;    s->pborctl = 0x7ffd;    s->rcc = 0x078e3ac0;    s->rcgc[0] = 1;    s->scgc[0] = 1;    s->dcgc[0] = 1;}static void stellaris_sys_init(uint32_t base, qemu_irq irq,                               stellaris_board_info * board,                               uint8_t *macaddr){    int iomemtype;    ssys_state *s;    s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));    s->base = base;    s->irq = irq;    s->board = board;    /* Most devices come preprogrammed with a MAC address in the user data. */    s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);    s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);    iomemtype = cpu_register_io_memory(0, ssys_readfn,                                       ssys_writefn, s);    cpu_register_physical_memory(base, 0x00001000, iomemtype);    ssys_reset(s);    /* ??? Save/restore.  */}/* I2C controller.  */typedef struct {    i2c_bus *bus;    qemu_irq irq;    uint32_t base;    uint32_t msa;    uint32_t mcs;    uint32_t mdr;    uint32_t mtpr;    uint32_t mimr;    uint32_t mris;    uint32_t mcr;} stellaris_i2c_state;#define STELLARIS_I2C_MCS_BUSY    0x01#define STELLARIS_I2C_MCS_ERROR   0x02#define STELLARIS_I2C_MCS_ADRACK  0x04#define STELLARIS_I2C_MCS_DATACK  0x08#define STELLARIS_I2C_MCS_ARBLST  0x10#define STELLARIS_I2C_MCS_IDLE    0x20#define STELLARIS_I2C_MCS_BUSBSY  0x40static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset){    stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;    offset -= s->base;    switch (offset) {    case 0x00: /* MSA */        return s->msa;    case 0x04: /* MCS */        /* We don't emulate timing, so the controller is never busy.  */        return s->mcs | STELLARIS_I2C_MCS_IDLE;    case 0x08: /* MDR */        return s->mdr;    case 0x0c: /* MTPR */        return s->mtpr;    case 0x10: /* MIMR */        return s->mimr;    case 0x14: /* MRIS */        return s->mris;    case 0x18: /* MMIS */        return s->mris & s->mimr;    case 0x20: /* MCR */        return s->mcr;    default:        cpu_abort(cpu_single_env, "strllaris_i2c_read: Bad offset 0x%x\n",                  (int)offset);        return 0;    }}static void stellaris_i2c_update(stellaris_i2c_state *s){    int level;    level = (s->mris & s->mimr) != 0;    qemu_set_irq(s->irq, level);}static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,                                uint32_t value){    stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;    offset -= s->base;    switch (offset) {    case 0x00: /* MSA */        s->msa = value & 0xff;        break;    case 0x04: /* MCS */        if ((s->mcr & 0x10) == 0) {            /* Disabled.  Do nothing.  */            break;        }        /* Grab the bus if this is starting a transfer.  */        if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {            if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {                s->mcs |= STELLARIS_I2C_MCS_ARBLST;            } else {                s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;                s->mcs |= STELLARIS_I2C_MCS_BUSBSY;            }        }        /* If we don't have the bus then indicate an error.  */        if (!i2c_bus_busy(s->bus)                || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {            s->mcs |= STELLARIS_I2C_MCS_ERROR;            break;        }        s->mcs &= ~STELLARIS_I2C_MCS_ERROR;        if (value & 1) {            /* Transfer a byte.  */            /* TODO: Handle errors.  */            if (s->msa & 1) {                /* Recv */                s->mdr = i2c_recv(s->bus) & 0xff;            } else {                /* Send */                i2c_send(s->bus, s->mdr);            }            /* Raise an interrupt.  */            s->mris |= 1;        }        if (value & 4) {            /* Finish transfer.  */            i2c_end_transfer(s->bus);            s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;        }        break;    case 0x08: /* MDR */        s->mdr = value & 0xff;        break;    case 0x0c: /* MTPR */        s->mtpr = value & 0xff;        break;    case 0x10: /* MIMR */        s->mimr = 1;        break;    case 0x1c: /* MICR */        s->mris &= ~value;        break;    case 0x20: /* MCR */        if (value & 1)            cpu_abort(cpu_single_env,                      "stellaris_i2c_write: Loopback not implemented\n");        if (value & 0x20)            cpu_abort(cpu_single_env,                      "stellaris_i2c_write: Slave mode not implemented\n");        s->mcr = value & 0x31;        break;    default:        cpu_abort(cpu_single_env, "stellaris_i2c_write: Bad offset 0x%x\n",                  (int)offset);    }    stellaris_i2c_update(s);}static void stellaris_i2c_reset(stellaris_i2c_state *s){    if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)        i2c_end_transfer(s->bus);    s->msa = 0;    s->mcs = 0;    s->mdr = 0;    s->mtpr = 1;    s->mimr = 0;    s->mris = 0;    s->mcr = 0;    stellaris_i2c_update(s);}static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {   stellaris_i2c_read,   stellaris_i2c_read,   stellaris_i2c_read};static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {   stellaris_i2c_write,   stellaris_i2c_write,   stellaris_i2c_write};static void stellaris_i2c_init(uint32_t base, qemu_irq irq, i2c_bus *bus){    stellaris_i2c_state *s;    int iomemtype;    s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));    s->base = base;    s->irq = irq;    s->bus = bus;    iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,                                       stellaris_i2c_writefn, s);    cpu_register_physical_memory(base, 0x00001000, iomemtype);    /* ??? For now we only implement the master interface.  */    stellaris_i2c_reset(s);}/* Analogue to Digital Converter.  This is only partially implemented,   enough for applications that use a combined ADC and timer tick.  */#define STELLARIS_ADC_EM_CONTROLLER 0#define STELLARIS_ADC_EM_COMP       1#define STELLARIS_ADC_EM_EXTERNAL   4#define STELLARIS_ADC_EM_TIMER      5#define STELLARIS_ADC_EM_PWM0       6#define STELLARIS_ADC_EM_PWM1       7#define STELLARIS_ADC_EM_PWM2       8#define STELLARIS_ADC_FIFO_EMPTY    0x0100#define STELLARIS_ADC_FIFO_FULL     0x1000typedef struct{    uint32_t base;    uint32_t actss;    uint32_t ris;    uint32_t im;    uint32_t emux;    uint32_t ostat;    uint32_t ustat;    uint32_t sspri;    uint32_t sac;    struct {        uint32_t state;        uint32_t data[16];    } fifo[4];    uint32_t ssmux[4];    uint32_t ssctl[4];    qemu_irq irq;} stellaris_adc_state;static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n){    int tail;    tail = s->fifo[n].state & 0xf;    if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {        s->ustat |= 1 << n;    } else {        s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);        s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;        if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))            s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;