#define IOMMU_CMD_BUFFER_HEAD_MASK		0x0007FFF0#define IOMMU_CMD_BUFFER_HEAD_SHIFT		4#define IOMMU_CMD_BUFFER_TAIL_MASK		0x0007FFF0#define IOMMU_CMD_BUFFER_TAIL_SHIFT		4#define IOMMU_CMD_BUFFER_ENTRY_SIZE			16#define IOMMU_CMD_BUFFER_POWER_OF2_ENTRIES_PER_PAGE	8#define IOMMU_CMD_BUFFER_U32_PER_ENTRY 	(IOMMU_CMD_BUFFER_ENTRY_SIZE / 4)#define IOMMU_CMD_OPCODE_MASK			0xF0000000#define IOMMU_CMD_OPCODE_SHIFT			28#define IOMMU_CMD_COMPLETION_WAIT		0x1#define IOMMU_CMD_INVALIDATE_DEVTAB_ENTRY	0x2#define IOMMU_CMD_INVALIDATE_IOMMU_PAGES	0x3#define IOMMU_CMD_INVALIDATE_IOTLB_PAGES	0x4#define IOMMU_CMD_INVALIDATE_INT_TABLE		0x5/* COMPLETION_WAIT command */#define IOMMU_COMP_WAIT_DATA_BUFFER_SIZE	8#define IOMMU_COMP_WAIT_DATA_BUFFER_ALIGNMENT	8#define IOMMU_COMP_WAIT_S_FLAG_MASK		0x00000001#define IOMMU_COMP_WAIT_S_FLAG_SHIFT		0#define IOMMU_COMP_WAIT_I_FLAG_MASK		0x00000002#define IOMMU_COMP_WAIT_I_FLAG_SHIFT		1#define IOMMU_COMP_WAIT_F_FLAG_MASK		0x00000004#define IOMMU_COMP_WAIT_F_FLAG_SHIFT		2#define IOMMU_COMP_WAIT_ADDR_LOW_MASK		0xFFFFFFF8#define IOMMU_COMP_WAIT_ADDR_LOW_SHIFT		3#define IOMMU_COMP_WAIT_ADDR_HIGH_MASK		0x000FFFFF#define IOMMU_COMP_WAIT_ADDR_HIGH_SHIFT		0/* INVALIDATE_IOMMU_PAGES command */#define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK	0x0000FFFF#define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_SHIFT	0#define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK	0x00000001#define IOMMU_INV_IOMMU_PAGES_S_FLAG_SHIFT	0#define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK	0x00000002#define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_SHIFT	1#define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK	0xFFFFF000#define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_SHIFT	12#define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK	0xFFFFFFFF#define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_SHIFT	0/* INVALIDATE_DEVTAB_ENTRY command */#define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK   0x0000FFFF#define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_SHIFT  0/* INVALIDATE_INTERRUPT_TABLE command */#define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK   0x0000FFFF#define IOMMU_INV_INT_TABLE_DEVICE_ID_SHIFT  0/* Event Log */#define IOMMU_EVENT_LOG_BASE_LOW_OFFSET		0x10#define IOMMU_EVENT_LOG_BASE_HIGH_OFFSET	0x14#define IOMMU_EVENT_LOG_HEAD_OFFSET		0x2010#define IOMMU_EVENT_LOG_TAIL_OFFSET		0x2018#define IOMMU_EVENT_LOG_BASE_LOW_MASK		0xFFFFF000#define IOMMU_EVENT_LOG_BASE_LOW_SHIFT		12#define IOMMU_EVENT_LOG_BASE_HIGH_MASK		0x000FFFFF#define IOMMU_EVENT_LOG_BASE_HIGH_SHIFT		0#define IOMMU_EVENT_LOG_LENGTH_MASK		0x0F000000#define IOMMU_EVENT_LOG_LENGTH_SHIFT		24#define IOMMU_EVENT_LOG_HEAD_MASK		0x0007FFF0#define IOMMU_EVENT_LOG_HEAD_SHIFT		4#define IOMMU_EVENT_LOG_TAIL_MASK		0x0007FFF0#define IOMMU_EVENT_LOG_TAIL_SHIFT		4#define IOMMU_EVENT_LOG_ENTRY_SIZE 			16#define IOMMU_EVENT_LOG_POWER_OF2_ENTRIES_PER_PAGE	8#define IOMMU_EVENT_LOG_U32_PER_ENTRY	(IOMMU_EVENT_LOG_ENTRY_SIZE / 4)#define IOMMU_EVENT_CODE_MASK			0xF0000000#define IOMMU_EVENT_CODE_SHIFT			28#define IOMMU_EVENT_ILLEGAL_DEV_TABLE_ENTRY	0x1#define IOMMU_EVENT_IO_PAGE_FALT		0x2#define IOMMU_EVENT_DEV_TABLE_HW_ERROR		0x3#define IOMMU_EVENT_PAGE_TABLE_HW_ERROR		0x4#define IOMMU_EVENT_ILLEGAL_COMMAND_ERROR	0x5#define IOMMU_EVENT_COMMAND_HW_ERROR		0x6#define IOMMU_EVENT_IOTLB_INV_TIMEOUT		0x7#define IOMMU_EVENT_INVALID_DEV_REQUEST		0x8#define IOMMU_EVENT_DOMAIN_ID_MASK           0x0000FFFF#define IOMMU_EVENT_DOMAIN_ID_SHIFT          0#define IOMMU_EVENT_DEVICE_ID_MASK           0x0000FFFF#define IOMMU_EVENT_DEVICE_ID_SHIFT          0/* Control Register */#define IOMMU_CONTROL_MMIO_OFFSET			0x18#define IOMMU_CONTROL_TRANSLATION_ENABLE_MASK		0x00000001#define IOMMU_CONTROL_TRANSLATION_ENABLE_SHIFT		0#define IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_MASK	0x00000002#define IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT	1#define IOMMU_CONTROL_EVENT_LOG_ENABLE_MASK		0x00000004#define IOMMU_CONTROL_EVENT_LOG_ENABLE_SHIFT		2#define IOMMU_CONTROL_EVENT_LOG_INT_MASK		0x00000008#define IOMMU_CONTROL_EVENT_LOG_INT_SHIFT		3#define IOMMU_CONTROL_COMP_WAIT_INT_MASK		0x00000010#define IOMMU_CONTROL_COMP_WAIT_INT_SHIFT		4#define IOMMU_CONTROL_TRANSLATION_CHECK_DISABLE_MASK	0x00000020#define IOMMU_CONTROL_TRANSLATION_CHECK_DISABLE_SHIFT	5#define IOMMU_CONTROL_INVALIDATION_TIMEOUT_MASK		0x000000C0#define IOMMU_CONTROL_INVALIDATION_TIMEOUT_SHIFT	6#define IOMMU_CONTROL_PASS_POSTED_WRITE_MASK		0x00000100#define IOMMU_CONTROL_PASS_POSTED_WRITE_SHIFT		8#define IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_MASK	0x00000200#define IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT	9#define IOMMU_CONTROL_COHERENT_MASK			0x00000400#define IOMMU_CONTROL_COHERENT_SHIFT			10#define IOMMU_CONTROL_ISOCHRONOUS_MASK			0x00000800#define IOMMU_CONTROL_ISOCHRONOUS_SHIFT			11#define IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_MASK	0x00001000#define IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT	12#define IOMMU_CONTROL_RESTART_MASK			0x80000000#define IOMMU_CONTROL_RESTART_SHIFT			31/* Exclusion Register */#define IOMMU_EXCLUSION_BASE_LOW_OFFSET		0x20#define IOMMU_EXCLUSION_BASE_HIGH_OFFSET	0x24#define IOMMU_EXCLUSION_LIMIT_LOW_OFFSET	0x28#define IOMMU_EXCLUSION_LIMIT_HIGH_OFFSET	0x2C#define IOMMU_EXCLUSION_BASE_LOW_MASK		0xFFFFF000#define IOMMU_EXCLUSION_BASE_LOW_SHIFT		12#define IOMMU_EXCLUSION_BASE_HIGH_MASK		0xFFFFFFFF#define IOMMU_EXCLUSION_BASE_HIGH_SHIFT		0#define IOMMU_EXCLUSION_RANGE_ENABLE_MASK	0x00000001#define IOMMU_EXCLUSION_RANGE_ENABLE_SHIFT	0#define IOMMU_EXCLUSION_ALLOW_ALL_MASK		0x00000002#define IOMMU_EXCLUSION_ALLOW_ALL_SHIFT		1#define IOMMU_EXCLUSION_LIMIT_LOW_MASK		0xFFFFF000#define IOMMU_EXCLUSION_LIMIT_LOW_SHIFT		12#define IOMMU_EXCLUSION_LIMIT_HIGH_MASK		0xFFFFFFFF#define IOMMU_EXCLUSION_LIMIT_HIGH_SHIFT	0/* Status Register*/#define IOMMU_STATUS_MMIO_OFFSET		0x2020#define IOMMU_STATUS_EVENT_OVERFLOW_MASK	0x00000001#define IOMMU_STATUS_EVENT_OVERFLOW_SHIFT	0#define IOMMU_STATUS_EVENT_LOG_INT_MASK		0x00000002#define IOMMU_STATUS_EVENT_LOG_INT_SHIFT	1#define IOMMU_STATUS_COMP_WAIT_INT_MASK		0x00000004#define IOMMU_STATUS_COMP_WAIT_INT_SHIFT	2#define IOMMU_STATUS_EVENT_LOG_RUN_MASK		0x00000008#define IOMMU_STATUS_EVENT_LOG_RUN_SHIFT	3#define IOMMU_STATUS_CMD_BUFFER_RUN_MASK	0x00000010#define IOMMU_STATUS_CMD_BUFFER_RUN_SHIFT	4/* I/O Page Table */#define IOMMU_PAGE_TABLE_ENTRY_SIZE	8#define IOMMU_PAGE_TABLE_U32_PER_ENTRY	(IOMMU_PAGE_TABLE_ENTRY_SIZE / 4)#define IOMMU_PAGE_TABLE_ALIGNMENT	4096#define IOMMU_PTE_PRESENT_MASK			0x00000001#define IOMMU_PTE_PRESENT_SHIFT			0#define IOMMU_PTE_NEXT_LEVEL_MASK		0x00000E00#define IOMMU_PTE_NEXT_LEVEL_SHIFT		9#define IOMMU_PTE_ADDR_LOW_MASK			0xFFFFF000#define IOMMU_PTE_ADDR_LOW_SHIFT		12#define IOMMU_PTE_ADDR_HIGH_MASK		0x000FFFFF#define IOMMU_PTE_ADDR_HIGH_SHIFT		0#define IOMMU_PTE_U_MASK			0x08000000#define IOMMU_PTE_U_SHIFT			7#define IOMMU_PTE_FC_MASK			0x10000000#define IOMMU_PTE_FC_SHIFT			28#define IOMMU_PTE_IO_READ_PERMISSION_MASK	0x20000000#define IOMMU_PTE_IO_READ_PERMISSION_SHIFT	29#define IOMMU_PTE_IO_WRITE_PERMISSION_MASK	0x40000000#define IOMMU_PTE_IO_WRITE_PERMISSION_SHIFT	30/* I/O Page Directory */#define IOMMU_PAGE_DIRECTORY_ENTRY_SIZE		8#define IOMMU_PAGE_DIRECTORY_ALIGNMENT		4096#define IOMMU_PDE_PRESENT_MASK			0x00000001#define IOMMU_PDE_PRESENT_SHIFT			0#define IOMMU_PDE_NEXT_LEVEL_MASK		0x00000E00#define IOMMU_PDE_NEXT_LEVEL_SHIFT		9#define IOMMU_PDE_ADDR_LOW_MASK			0xFFFFF000#define IOMMU_PDE_ADDR_LOW_SHIFT		12#define IOMMU_PDE_ADDR_HIGH_MASK		0x000FFFFF#define IOMMU_PDE_ADDR_HIGH_SHIFT		0#define IOMMU_PDE_IO_READ_PERMISSION_MASK	0x20000000#define IOMMU_PDE_IO_READ_PERMISSION_SHIFT	29#define IOMMU_PDE_IO_WRITE_PERMISSION_MASK	0x40000000#define IOMMU_PDE_IO_WRITE_PERMISSION_SHIFT	30/* Paging modes */#define IOMMU_PAGING_MODE_DISABLED	0x0#define IOMMU_PAGING_MODE_LEVEL_0	0x0#define IOMMU_PAGING_MODE_LEVEL_1	0x1#define IOMMU_PAGING_MODE_LEVEL_2	0x2#define IOMMU_PAGING_MODE_LEVEL_3	0x3#define IOMMU_PAGING_MODE_LEVEL_4	0x4#define IOMMU_PAGING_MODE_LEVEL_5	0x5#define IOMMU_PAGING_MODE_LEVEL_6	0x6#define IOMMU_PAGING_MODE_LEVEL_7	0x7/* Flags */#define IOMMU_CONTROL_DISABLED	0#define IOMMU_CONTROL_ENABLED	1#define MMIO_PAGES_PER_IOMMU        (IOMMU_MMIO_REGION_LENGTH / PAGE_SIZE_4K)#define IOMMU_PAGES                 (MMIO_PAGES_PER_IOMMU * MAX_AMD_IOMMUS)#define DEFAULT_DOMAIN_ADDRESS_WIDTH    48#define MAX_AMD_IOMMUS                  32#define IOMMU_PAGE_TABLE_LEVEL_3        3#define IOMMU_PAGE_TABLE_LEVEL_4        4#define IOMMU_IO_WRITE_ENABLED          1#define IOMMU_IO_READ_ENABLED           1#define HACK_BIOS_SETTINGS                  0/* interrupt remapping table */#define INT_REMAP_INDEX_DM_MASK         0x1C00#define INT_REMAP_INDEX_DM_SHIFT        10#define INT_REMAP_INDEX_VECTOR_MASK     0x3FC#define INT_REMAP_INDEX_VECTOR_SHIFT    2#define INT_REMAP_ENTRY_REMAPEN_MASK    0x00000001#define INT_REMAP_ENTRY_REMAPEN_SHIFT   0#define INT_REMAP_ENTRY_SUPIOPF_MASK    0x00000002#define INT_REMAP_ENTRY_SUPIOPF_SHIFT   1#define INT_REMAP_ENTRY_INTTYPE_MASK    0x0000001C#define INT_REMAP_ENTRY_INTTYPE_SHIFT   2#define INT_REMAP_ENTRY_REQEOI_MASK     0x00000020#define INT_REMAP_ENTRY_REQEOI_SHIFT    5#define INT_REMAP_ENTRY_DM_MASK         0x00000040#define INT_REMAP_ENTRY_DM_SHIFT        6#define INT_REMAP_ENTRY_DEST_MAST       0x0000FF00#define INT_REMAP_ENTRY_DEST_SHIFT      8#define INT_REMAP_ENTRY_VECTOR_MASK     0x00FF0000#define INT_REMAP_ENTRY_VECTOR_SHIFT    16#endif /* _ASM_X86_64_AMD_IOMMU_DEFS_H */