?? lpregs.h
字號:
//--------------------------------------------------------------------------
//
// Filename: lpregs.h
//
// Description: Include file which defines the CYRF6936 registers
//
//--------------------------------------------------------------------------
// WirelessUSB LP Radio Driver Version 1.0
// $Revision: 3 $
//--------------------------------------------------------------------------
//
// Copyright 2003-2006, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
// and is protected by and subject to worldwide patent protection (United
// States and foreign), United States copyright laws and international
// treaty provisions. Cypress hereby grants to licensee a personal,
// non-exclusive, non-transferable license to copy, use, modify, create
// derivative works of, and compile the Cypress Source Code and derivative
// works for the sole purpose of creating custom software in support of
// licensee product to be used only in conjunction with a Cypress integrated
// circuit as specified in the applicable agreement. Any reproduction,
// modification, translation, compilation, or representation of this
// software except as specified above is prohibited without the express
// written permission of Cypress.
//
// Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
// Cypress reserves the right to make changes without further notice to the
// materials described herein. Cypress does not assume any liability arising
// out of the application or use of any product or circuit described herein.
// Cypress does not authorize its products for use as critical components in
// life-support systems where a malfunction or failure may reasonably be
// expected to result in significant injury to the user. The inclusion of
// Cypress' product in a life-support systems application implies that the
// manufacturer assumes all risk of such use and in doing so indemnifies
// Cypress against all charges.
//
// Use may be limited by and subject to the applicable Cypress software
// license agreement.
//
//--------------------------------------------------------------------------
#ifndef _LpRegs_h_
#define _LpRegs_h_
// -------------------------------
// Channel register
// -------------------------------
#define CHANNEL_ADR 0x00
#define CHANNEL_RST 0x48
#define CHANNEL_MSK 0x7F
#define CHANNEL_MAX 0x62
#define CHANNEL_MIN 0x00
#define CHANNEL_2P498_GHZ 0x62
#define CHANNEL_2P4_GHZ 0x00
// -------------------------------
// TX Length register
// -------------------------------
#define TX_LENGTH_ADR 0x01
#define TX_LENGTH_RST 0x00
#define TX_LENGTH_MSK 0xFF
// -------------------------------
// TX Control register
// -------------------------------
#define TX_CTRL_ADR 0x02
#define TX_CTRL_RST 0x03
// See TX_IRQ for remaining bit position definitions
// TX_CTRL bit masks
#define TX_GO 0x80
#define TX_CLR 0x40
// -------------------------------
// TX Configuration register
// -------------------------------
#define TX_CFG_ADR 0x03
#define TX_CFG_RST 0x05
// separate bit field masks
#define TX_DATCODE_LEN_MSK 0x20
#define TX_DATMODE_MSK 0x18
#define PA_VAL_MSK 0x07
// DATCODE_LEN register masks
#define DATCODE_LEN_64 0x20
#define DATCODE_LEN_32 0x00
// DATMODE register masks
#define DATMODE_1MBPS 0x00
#define DATMODE_8DR 0x08
#define DATMODE_DDR 0x10
#define DATMODE_SDR 0x18
// PA_SET register masks
#define PA_N30_DBM 0x00
#define PA_N25_DBM 0x01
#define PA_N20_DBM 0x02
#define PA_N15_DBM 0x03
#define PA_N10_DBM 0x04
#define PA_N5_DBM 0x05
#define PA_0_DBM 0x06
#define PA_4_DBM 0x07
// -------------------------------
// TX IRQ Status register
// -------------------------------
#define TX_IRQ_STATUS_ADR 0x04
// TX_IRQ bit masks
#define XS_IRQ 0x80
#define LV_IRQ 0x40
#define TXB15_IRQ 0x20
#define TXB8_IRQ 0x10
#define TXB0_IRQ 0x08
#define TXBERR_IRQ 0x04
#define TXC_IRQ 0x02
#define TXE_IRQ 0x01
// -------------------------------
// RX Control register
// -------------------------------
#define RX_CTRL_ADR 0x05
#define RX_CTRL_RST 0x07
// See RX_IRQ register for bit positions definitions also used for this register
// RX_CTRL bit masks
#define RX_GO 0x80
// -------------------------------
// RX Configuration register
// -------------------------------
#define RX_CFG_ADR 0x06
#define RX_CFG_RST 0x92
#define AUTO_AGC_EN 0x80
#define LNA_EN 0x40
#define ATT_EN 0x20
#define HI 0x10
#define LO 0x00
#define FASTTURN_EN 0x08
#define RXOW_EN 0x02
#define VLD_EN 0x01
// -------------------------------
// RX IRQ register
// -------------------------------
#define RX_IRQ_STATUS_ADR 0x07
// There is no default value for this register.
// RX_IRQ bit masks
#define RXOW_IRQ 0x80
#define SOFDET_IRQ 0x40
#define RXB16_IRQ 0x20
#define RXB8_IRQ 0x10
#define RXB1_IRQ 0x08
#define RXBERR_IRQ 0x04
#define RXC_IRQ 0x02
#define RXE_IRQ 0x01
// -------------------------------
// RX Status register
// -------------------------------
#define RX_STATUS_ADR 0x08
// There is no default value for this register.
// single flag bits & multi-bit-field masks
#define RX_ACK 0x80
#define RX_PKTERR 0x40
#define RX_EOPERR 0x20
#define RX_CRC0 0x10
#define RX_BAD_CRC 0x08
#define RX_DATCODE_LEN 0x04
#define RX_DATMODE_MSK 0x03
// -------------------------------
// RX Count register
// -------------------------------
#define RX_COUNT_ADR 0x09
#define RX_COUNT_RST 0x00
#define RX_COUNT_MSK 0xFF
// -------------------------------
// RX Length Field register
// -------------------------------
#define RX_LENGTH_ADR 0x0A
#define RX_LENGTH_RST 0x00
#define RX_LENGTH_MSK 0xFF
// -------------------------------
// Power Control register
// -------------------------------
#define PWR_CTRL_ADR 0x0B
#define PWR_CTRL_RST 0xA0
// single flag bits & multi-bit-field masks
#define PMU_EN 0x80
#define LV_IRQ_EN 0x40
#define PMU_SEN 0x20
#define PFET_OFF 0x10
#define LV_IRQ_TH_MSK 0x0C
#define PMU_OUTV_MSK 0x03
// LV_IRQ_TH values
#define LV_IRQ_TH_1P8_V 0x0C
#define LV_IRQ_TH_2P0_V 0x08
#define LV_IRQ_TH_2P2_V 0x04
#define LV_IRQ_TH_PMU_OUTV 0x00
// PMU_OUTV values
#define PMU_OUTV_2P4 0x03
#define PMU_OUTV_2P5 0x02
#define PMU_OUTV_2P6 0x01
#define PMU_OUTV_2P7 0x00
// -------------------------------
// Crystal Control register
// -------------------------------
#define XTAL_CTRL_ADR 0x0C
#define XTAL_CTRL_RST 0x04
// single flag bits & multi-bit-field masks
#define XOUT_FNC_MSK 0xC0
#define XS_IRQ_EN 0x20
#define XOUT_FREQ_MSK 0x07
// XOUT_FNC values
#define XOUT_FNC_XOUT_FREQ 0x00
#define XOUT_FNC_PA_N 0x40
#define XOUT_FNC_RAD_STREAM 0x80
#define XOUT_FNC_GPIO 0xC0
// XOUT_FREQ values
#define XOUT_FREQ_12MHZ 0x00
#define XOUT_FREQ_6MHZ 0x01
#define XOUT_FREQ_3MHZ 0x02
#define XOUT_FREQ_1P5MHZ 0x03
#define XOUT_FREQ_P75MHZ 0x04
// -------------------------------
// I/O Configuration register
// -------------------------------
#define IO_CFG_ADR 0x0D
#define IO_CFG_RST 0x00
#define IO_CFG_MSK 0xFF
// single flag bits & multi-bit-field masks
#define IRQ_OD 0x80
#define IRQ_POL 0x40
#define MISO_OD 0x20
#define XOUT_OD 0x10
#define PACTL_OD 0x08
#define PACTL_GPIO 0x04
#define SPI_3_PIN 0x02
#define IRQ_GPIO 0x01
// -------------------------------
// GPIO Control register
// -------------------------------
#define GPIO_CTRL_ADR 0x0E
#define GPIO_CTRL_RST 0x00
#define GPIO_CTRL_MSK 0xF0
// single flag bits & multi-bit-field masks
#define XOUT_OP 0x80
#define MISO_OP 0x40
#define PACTL_OP 0x20
#define IRQ_OP 0x10
#define XOUT_IP 0x08
#define MISO_IP 0x04
#define PACTL_IP 0x02
#define IRQ_IP 0x01
// -------------------------------
// Transaction Configuration register
// -------------------------------
#define XACT_CFG_ADR 0x0F
#define XACT_CFG_RST 0x80
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -