;--------------------------------------------------------------------------
;
;  Filename:     lpregs.inc
;
;  Description:  Include file which defines the CYRF6936 registers
;
;--------------------------------------------------------------------------
; WirelessUSB LP Radio Driver Version 1.0
; $Revision: 3 $
;--------------------------------------------------------------------------
;
; Copyright 2005-2006, Cypress Semiconductor Corporation.
;
; This software is owned by Cypress Semiconductor Corporation (Cypress)
; and is protected by and subject to worldwide patent protection (United
; States and foreign), United States copyright laws and international
; treaty provisions. Cypress hereby grants to licensee a personal,
; non-exclusive, non-transferable license to copy, use, modify, create
; derivative works of, and compile the Cypress Source Code and derivative
; works for the sole purpose of creating custom software in support of
; licensee product to be used only in conjunction with a Cypress integrated
; circuit as specified in the applicable agreement. Any reproduction,
; modification, translation, compilation, or representation of this
; software except as specified above is prohibited without the express
; written permission of Cypress.
;
; Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
; WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
; Cypress reserves the right to make changes without further notice to the
; materials described herein. Cypress does not assume any liability arising
; out of the application or use of any product or circuit described herein.
; Cypress does not authorize its products for use as critical components in
; life-support systems where a malfunction or failure may reasonably be
; expected to result in significant injury to the user. The inclusion of
; Cypress' product in a life-support systems application implies that the
; manufacturer assumes all risk of such use and in doing so indemnifies
; Cypress against all charges.
;
; Use may be limited by and subject to the applicable Cypress software
; license agreement.
;
;--------------------------------------------------------------------------


; -------------------------------
; Channel register
; -------------------------------
CHANNEL_ADR:                                    equ 0x00
CHANNEL_RST:                                    equ 0x48
CHANNEL_MSK:                                    equ 0x7f

CHANNEL_MAX:                                    equ 0x62
CHANNEL_MIN:                                    equ 0x00
CHANNEL_2P498_GHZ:                              equ 0x62
CHANNEL_2P4_GHZ:                                equ 0x00


; -------------------------------
; TX Length register
; -------------------------------
TX_LENGTH_ADR:                                  equ 0x01
TX_LENGTH_RST:                                  equ 0x00
TX_LENGTH_MSK:                                  equ 0xff


; -------------------------------
; TX Control register
; -------------------------------
TX_CTRL_ADR:                                    equ 0x02
TX_CTRL_RST:                                    equ 0x03

; See TX_IRQ for remaining bit position definitions

; TX_CTRL bit masks
TX_GO:                                          equ 0x80
TX_CLR:                                         equ 0x40


; -------------------------------
; TX Configuration register
; -------------------------------
TX_CFG_ADR:                                     equ 0x03
TX_CFG_RST:                                     equ 0x05

; separate bit field masks
TX_DATCODE_LEN_MSK:                             equ 0x20
TX_DATMODE_MSK:                                 equ 0x18
PA_VAL_MSK:                                     equ 0x07

; DATCODE_LEN register masks
DATCODE_LEN_64:                                 equ 0x20
DATCODE_LEN_32:                                 equ 0x00

; DATMODE register masks
DATMODE_1MBPS:                                  equ 0x00
DATMODE_8DR:                                    equ 0x08
DATMODE_DDR:                                    equ 0x10
DATMODE_SDR:                                    equ 0x18

; PA_SET register masks
PA_N30_DBM:                                     equ 0x00
PA_N25_DBM:                                     equ 0x01
PA_N20_DBM:                                     equ 0x02
PA_N15_DBM:                                     equ 0x03
PA_N10_DBM:                                     equ 0x04
PA_N5_DBM:                                      equ 0x05
PA_0_DBM:                                       equ 0x06
PA_4_DBM:                                       equ 0x07


; -------------------------------
; TX IRQ Status register
; -------------------------------
TX_IRQ_STATUS_ADR:                              equ 0x04

; TX_IRQ bit masks
XS_IRQ:                                         equ 0x80
LV_IRQ:                                         equ 0x40
TXB15_IRQ:                                      equ 0x20
TXB8_IRQ:                                       equ 0x10
TXB0_IRQ:                                       equ 0x08
TXBERR_IRQ:                                     equ 0x04
TXC_IRQ:                                        equ 0x02
TXE_IRQ:                                        equ 0x01


; -------------------------------
; RX Control register
; -------------------------------
RX_CTRL_ADR:                                    equ 0x05
RX_CTRL_RST:                                    equ 0x07

; See RX_IRQ register for bit positions definitions also used for this register

; RX_CTRL bit masks
RX_GO:                                          equ 0x80


; -------------------------------
; RX Configuration register
; -------------------------------
RX_CFG_ADR:                                     equ 0x06
RX_CFG_RST:                                     equ 0x92

AUTO_AGC_EN:                                    equ 0x80
LNA_EN:                                         equ 0x40
ATT_EN:                                         equ 0x20
HI:                                             equ 0x10
LO:                                             equ 0x00
FASTTURN_EN:                                    equ 0x08
RXOW_EN:                                        equ 0x02
VLD_EN:                                         equ 0x01


; -------------------------------
; RX IRQ register
; -------------------------------
RX_IRQ_STATUS_ADR:                              equ 0x07
; There is no default value for this register.

; RX_IRQ bit masks
RXOW_IRQ:                                       equ 0x80
SOFDET_IRQ:                                     equ 0x40
RXB16_IRQ:                                      equ 0x20
RXB8_IRQ:                                       equ 0x10
RXB1_IRQ:                                       equ 0x08
RXBERR_IRQ:                                     equ 0x04
RXC_IRQ:                                        equ 0x02
RXE_IRQ:                                        equ 0x01


; -------------------------------
; RX Status register
; -------------------------------
RX_STATUS_ADR:                                  equ 0x08
// There is no default value for this register.

; single flag bits & multi-bit-field masks
RX_ACK:                                         equ 0x80
RX_PKTERR:                                      equ 0x40
RX_EOPERR:                                      equ 0x20
RX_CRC0:                                        equ 0x10
RX_BAD_CRC:                                     equ 0x08
RX_DATCODE_LEN:                                 equ 0x04
RX_DATMODE_MSK:                                 equ 0x03


; -------------------------------
; RX Count register
; -------------------------------
RX_COUNT_ADR:                                   equ 0x09
RX_COUNT_RST:                                   equ 0x00
RX_COUNT_MSK:                                   equ 0xff


; -------------------------------
; RX Length Field register
; -------------------------------
RX_LENGTH_ADR:                                  equ 0x0a
RX_LENGTH_RST:                                  equ 0x00
RX_LENGTH_MSK:                                  equ 0xff


; -------------------------------
; Power Control register
; -------------------------------
PWR_CTRL_ADR:                                   equ 0x0b
PWR_CTRL_RST:                                   equ 0xa0

; single flag bits & multi-bit-field masks
PMU_EN:                                         equ 0x80
LV_IRQ_EN:                                      equ 0x40
PMU_SEN:                                        equ 0x20
PFET_OFF:                                       equ 0x10
LV_IRQ_TH_MSK:                                  equ 0x0c
PMU_OUTV_MSK:                                   equ 0x03

; LV_IRQ_TH values
LV_IRQ_TH_1P8_V:                                equ 0x0C
LV_IRQ_TH_2P0_V:                                equ 0x08
LV_IRQ_TH_2P2_V:                                equ 0x04
LV_IRQ_TH_PMU_OUTV:                             equ 0x00

; PMU_OUTV values
PMU_OUTV_2P4:                                   equ 0x03
PMU_OUTV_2P5:                                   equ 0x02
PMU_OUTV_2P6:                                   equ 0x01
PMU_OUTV_2P7:                                   equ 0x00


; -------------------------------
; Crystal Control register
; -------------------------------
XTAL_CTRL_ADR:                                  equ 0x0c
XTAL_CTRL_RST:                                  equ 0x04

; single flag bits & multi-bit-field masks
XOUT_FNC_MSK:                                   equ 0xc0
XS_IRQ_EN:                                      equ 0x20
XOUT_FREQ_MSK:                                  equ 0x07

; XOUT_FNC values
XOUT_FNC_XOUT_FREQ:                             equ 0x00
XOUT_FNC_PA_N:                                  equ 0x40
XOUT_FNC_RAD_STREAM:                            equ 0x80
XOUT_FNC_GPIO:                                  equ 0xC0

; XOUT_FREQ values
XOUT_FREQ_12MHZ:                                equ 0x00
XOUT_FREQ_6MHZ:                                 equ 0x01
XOUT_FREQ_3MHZ:                                 equ 0x02
XOUT_FREQ_1P5MHZ:                               equ 0x03
XOUT_FREQ_P75MHZ:                               equ 0x04


; -------------------------------
; I/O Configuration register
; -------------------------------
IO_CFG_ADR:                                     equ 0x0d
IO_CFG_RST:                                     equ 0x00
IO_CFG_MSK:                                     equ 0xff

; single flag bits & multi-bit-field masks
IRQ_OD:                                         equ 0x80
IRQ_POL:                                        equ 0x40
MISO_OD:                                        equ 0x20
XOUT_OD:                                        equ 0x10
PACTL_OD:                                       equ 0x08
PACTL_GPIO:                                     equ 0x04
SPI_3_PIN:                                      equ 0x02
IRQ_GPIO:                                       equ 0x01


; -------------------------------
; GPIO Control register
; -------------------------------
GPIO_CTRL_ADR:                                  equ 0x0e
GPIO_CTRL_RST:                                  equ 0x00
GPIO_CTRL_MSK:                                  equ 0xf0

; single flag bits & multi-bit-field masks
XOUT_OP:                                        equ 0x80
MISO_OP:                                        equ 0x40
PACTL_OP:                                       equ 0x20
IRQ_OP:                                         equ 0x10
XOUT_IP:                                        equ 0x08
MISO_IP:                                        equ 0x04
PACTL_IP:                                       equ 0x02
IRQ_IP:                                         equ 0x01


; -------------------------------
; Transaction Configuration register
; -------------------------------
XACT_CFG_ADR:                                   equ 0x0f
XACT_CFG_RST:                                   equ 0x80