m25513cModel Technology
dD:\luoqiwu\FPGA\oytt
T_optV;76Q_]Pb?BBEFDPCgAGA`204 16 4 work decoder15_test_v fast 004 4 4 work glbl fast 0o-quiet -auto_acc_if_foreign -work work -L xilinxcorelib_ver -L unisims_vertExplicit 1OE;O;6.2b;35T_opt1VTY_9fLbSK^[WbbF4Mki`n104 16 4 work decoder15_test_v fast 0o-quiet -auto_acc_if_foreign -work work -L xilinxcorelib_ver -L unisims_vertExplicit 1OE;O;6.2b;35T_opt2V^dH^K7j9kMXHPliT;Je?V204 9 4 work decoder15 fast 004 4 4 work glbl fast 0o-quiet -auto_acc_if_foreign -work work -L xilinxcorelib_ver -L unisims_vertExplicit 1OE;O;6.2b;35vdecoder15I1O40235jIIJf7<G:z82dS3Vk[:QPAPMkAJ4iiWKa04`M0dD:\luoqiwu\FPGA\oyttw1210736144Fdecoder15.vL0 21Vk[:QPAPMkAJ4iiWKa04`M0OE;L;6.2b;35r131o+accvdecoder15_test_vIGiJ0KgoC>KI`0bk:H?=4V0V;10eNY<14CMTSSzZ6UYB;1dD:\luoqiwu\FPGA\oyttw1210733304Fdecoder15_test.vL0 25V;10eNY<14CMTSSzZ6UYB;1OE;L;6.2b;35r131o+accvglblI@25W]P_?R2MF58_YTL5O=0VnN]4Gon>inod6>M^M2[SV1dD:\luoqiwu\FPGA\oyttw1179523376FD:/Xilinx92i/verilog/src/glbl.vL0 5VnN]4Gon>inod6>M^M2[SV1OE;L;6.2b;35r131o+acc