?? tb_eth_top.v
字號:
*/
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h3); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h2); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h1); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0050, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0051, 1'b0, `UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0052, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0053, 1'b0, `BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0054, 1'b0, `UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0055, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0056, 1'b0, `UNICAST_WRONG_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
repeat(1000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
// WishboneRead({24'h04, (8'h0<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h1<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h2<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h3<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h4<<2)}, RxBD); // Read from TxBD register
for(jj=0; jj<3; jj=jj+1) // How many TxBD do we want to read?
begin
WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd); // Read from TxBD
$display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, jj, bd);
if(~bd[15]) // Ready = 0?
begin
WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read TxBD pointer
$display("\t\t\tRead TxBDPointer 0x=%x", pointer);
$write("\t\t\tData:");
for(ii=0; ii<bd[31:16]; ii=ii+4)
begin
WishboneReadData({pointer[31:2], 2'h0}+ii, data_in); // Read data from Tx Pointer
$write("\t0x%x", data_in);
end
end
end
for(jj=0; jj<3; jj=jj+1) // How many RxBD do we want to read?
begin
WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd); // Read from RxBD
$display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
if(~bd[15]) // Empty = 0?
begin
WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read RxBD pointer
$display("\t\t\tRead RxBDPointer 0x=%x", pointer);
$write("\t\t\tData:");
for(ii=0; ii<bd[31:16]+4; ii=ii+4)
begin
WishboneReadData({pointer[31:2], 2'h0} + ii, data_in); // Read data from Rx Pointer
$write("\t0x%x", data_in);
end
end
end
WishboneRead({22'h01, (10'h81<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h83<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h84<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h85<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}, data_in); // Read from RxBD register
#100000 $stop;
end
endtask //TestTxAndRx
task TestFullDuplex;
integer ii, jj;
integer data_in, bd, pointer;
integer addr;
begin
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
WishboneWrite(32'h0000a40b, {26'h0, `ETH_MODER_ADR<<2}); // CrcEn, Pad en, full duplex, reject broadcast, RxEn, TxEn
WishboneWrite(32'h00000002, {26'h0, `ETH_MAC_ADDR1_ADR<<2}); // MAC = 000203040506
WishboneWrite(32'h03040506, {26'h0, `ETH_MAC_ADDR0_ADR<<2});
initialize_txbd(5);
initialize_rxbd(6);
send_packet(48'h000123456789, 16'h0064);
/*
for(ii=0; ii<12; ii=ii+1) begin
addr = 32'h400 + ii*4;
WishboneRead(addr, data_in);
$display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, ii, data_in);
end
for(ii=0; ii<14; ii=ii+1) begin
addr = 32'h600 + ii*4;
WishboneRead(addr, data_in);
$display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, ii, data_in);
end
*/
// WishboneRead({22'h01, 10'b0}, data_in); // read back
// WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd); // Read from TxBD
/*
for(jj=0; jj<8; jj=jj+4)
WishboneWriteData(`TX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
for(jj=0; jj<8; jj=jj+4)
WishboneWriteData(`RX_BUF_BASE + jj, 32'h11111111, 4'hf); // Initializing data to ff
fork
begin
SendPacketX(16'h0064, 1'b0, 2'h1);
SendPacketX(16'h0065, 1'b0, 2'h2);
SendPacketX(16'h0066, 1'b0, 2'h3);
SendPacketX(16'h0067, 1'b0, 2'h0);
end
begin
ReceivePacketX(16'h0040, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacketX(16'h0041, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacketX(16'h0042, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacketX(16'h0043, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacketX(16'h0044, 1'b0, `UNICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
end
*/
//fork
/*
begin
repeat(4)
begin
wait(tb_eth_top.ethtop.wishbone.TxStatusWrite); // wait until tx status is written
@ (posedge WB_CLK_I)
#1;
end
end
*/
/*
begin
wait(tb_eth_top.ethtop.wishbone.RxStatusWrite); // wait until rx status is written
end
join
*/
/*
SendPacket(16'h0013, 1'b0);
SendPacket(16'h0014, 1'b0);
SendPacket(16'h0030, 1'b0);
SendPacket(16'h0031, 1'b0);
SendPacket(16'h0032, 1'b0);
SendPacket(16'h0033, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0045, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0017, 1'b0);
*/
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h3); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h2); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h1); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacketX(16'h0050, 1'b0, `MULTICAST_XFR, 2'h0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0050, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0051, 1'b0, `UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0052, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0053, 1'b0, `BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0054, 1'b0, `UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0055, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
// ReceivePacket(16'h0056, 1'b0, `UNICAST_WRONG_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
repeat(1000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
// WishboneRead({24'h04, (8'h0<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h1<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h2<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h3<<2)}, RxBD); // Read from TxBD register
// WishboneRead({24'h04, (8'h4<<2)}, RxBD); // Read from TxBD register
/*
for(jj=0; jj<3; jj=jj+1) // How many TxBD do we want to read?
begin
WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2)<<2)}, bd); // Read from TxBD
$display("\n(%0t)\t\tRead TxBD %0x = 0x%x", $time, jj, bd);
if(~bd[15]) // Ready = 0?
begin
WishboneRead({22'h01, ((10'h0+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read TxBD pointer
$display("\t\t\tRead TxBDPointer 0x=%x", pointer);
$write("\t\t\tData:");
for(ii=0; ii<bd[31:16]; ii=ii+4)
begin
WishboneReadData({pointer[31:2], 2'h0}+ii, data_in); // Read data from Tx Pointer
$write("\t0x%x", data_in);
end
end
end
for(jj=0; jj<3; jj=jj+1) // How many RxBD do we want to read?
begin
WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd); // Read from RxBD
$display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
if(~bd[15]) // Empty = 0?
begin
WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read RxBD pointer
$display("\t\t\tRead RxBDPointer 0x=%x", pointer);
$write("\t\t\tData:");
for(ii=0; ii<bd[31:16]+4; ii=ii+4)
begin
WishboneReadData({pointer[31:2], 2'h0} + ii, data_in); // Read data from Rx Pointer
$write("\t0x%x", data_in);
end
end
end
WishboneRead({22'h01, (10'h81<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h83<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h84<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h85<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}, data_in); // Read from RxBD register
*/
#100000 $stop;
end
endtask //TestFullDuplex
task initialize_txbd;
input [6:0] txbd_num;
integer i, j;
integer bd_status_addr, buf_addr, bd_ptr_addr;
for(i=0; i<txbd_num; i=i+1) begin
buf_addr = `TX_BUF_BASE + i * 32'h600;
bd_status_addr = `TX_BD_BASE + i * 8;
bd_ptr_addr = bd_status_addr + 4;
// Initializing BD - status
if(i==txbd_num-1)
WishboneWrite(32'h00007800, bd_status_addr); // last BD: + WRAP
else
WishboneWrite(32'h00005800, bd_status_addr); // IRQ + PAD + CRC
WishboneWrite(buf_addr, bd_ptr_addr); // Initializing BD - pointer
end
endtask // initialize_txbd
task initialize_rxbd;
input [6:0] rxbd_num;
integer i, j;
integer bd_status_addr, buf_addr, bd_ptr_addr;
for(i=0; i<rxbd_num; i=i+1) begin
buf_addr = `RX_BUF_BASE + i * 32'h600;
bd_status_addr = `RX_BD_BASE + i * 8;
bd_ptr_addr = bd_status_addr + 4;
// Initializing BD - status
if(i==rxbd_num-1)
WishboneWrite(32'h0000e000, bd_status_addr); // last BD: + WRAP
else
WishboneWrite(32'h0000c000, bd_status_addr); // IRQ + PAD + CRC
WishboneWrite(buf_addr, bd_ptr_addr); // Initializing BD - pointer
end
endtask // initialize_rxbd
reg [7:0] LateCollisionCounter;
reg EnableCollisionCounter;
// Making a late collision
initial
EnableCollisionCounter =0; // Collision = OFF
always @ (posedge MTxClk)
begin
if(tb_eth_top.ethtop.wishbone.TxStartFrm)
begin
LateCollisionCounter = 0;
end
else
if(EnableCollisionCounter)
LateCollisionCounter = LateCollisionCounter + 1;
end
// Making a late collision
always @ (posedge MTxClk)
begin
if(LateCollisionCounter==0)
MColl = 0;
else
if(LateCollisionCounter==150)
MColl = 1;
else
if(LateCollisionCounter==155)
begin
MColl = 0;
MCrs = 0;
EnableCollisionCounter=0;
LateCollisionCounter=1;
end
end
// Switching Carrier Sense ON and OFF
always @ (posedge MTxClk)
begin
wait(tb_eth_top.ethtop.wishbone.TxStartFrm);
MCrs=1;
wait(tb_eth_top.ethtop.wishbone.TxEndFrm || !MCrs);
MCrs=0;
end
task TestUnicast;
integer ii, jj;
integer data_in, bd, pointer;
begin
$display("\nBegin TestUnicast \n");
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
WishboneWrite(32'h0000204b, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, CrcEn, no Pad, r_IFG, promisc off, broadcast off
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
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