?? tb_eth_top.v
字號:
$display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
ReceivePacket(16'h0014, 1'b0,`UNICAST_XFR);
WishboneWrite(32'h03040506, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address
WishboneWrite(32'h00000002, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
$display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
ReceivePacket(16'h0015, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0019, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
WishboneRead({26'h0, `ETH_MODER_ADR}, data_in); // Read from MODER register
WishboneRead({22'h01, (10'h80<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h81<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h83<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h84<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h85<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h88<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h89<<2)}, data_in); // Read from RxBD register
for(jj=0; jj<5; jj=jj+1) // How many RxBD do we want to read?
begin
WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2)<<2)}, bd); // Read from RxBD
$display("\n(%0t)\t\tRead RxBD %0x = 0x%x", $time, jj, bd);
if(~bd[15]) // Empty = 0?
begin
WishboneRead({22'h01, ((10'h80+jj[4:0]*2'h2+1'h1)<<2)}, pointer); // Read RxBD pointer
$display("\t\t\tRead RxBDPointer 0x=%x", pointer);
$write("\t\t\tData:");
for(ii=0; ii<bd[31:16]+4; ii=ii+4)
begin
WishboneReadData({pointer[31:2], 2'h0} + ii, data_in); // Read data from Rx Pointer
$write("\t0x%x", data_in);
end
end
end
#100000 $stop;
$display("\nEnd TestUnicast \n");
end
endtask //TestUnicast
task TestMulticast;
integer data_in;
begin
$display("\nBegin TestMulticast \n");
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, CrcEn, No Pad, r_IFG, promiscuos off, broadcast enable
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
$display("\n This Multicast packet will be rejected by Hash Filter\n");
ReceivePacket(16'h0014, 1'b0,`MULTICAST_XFR);
WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
WishboneRead({26'h0, `ETH_HASH1_ADR, 2'h0}, data_in); // read back
$display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
ReceivePacket(16'h0015, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
WishboneRead({26'h0, `ETH_MODER_ADR}, data_in); // Read from MODER register
WishboneRead({22'h01, (10'h80<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h81<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h83<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h84<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h85<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}, data_in); // Read from RxBD register
$display("\nEnd TestMulticast \n");
#100000 $stop;
end
endtask //TestMulticast
task TestBroadcast;
integer data_in;
begin
$display("\n\n\nBegin TestBroadcast");
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
$display("\nThis Broadcast packet will be rejected, r_BRO = 1");
ReceivePacket(16'h0014, 1'b0,`BROADCAST_XFR);
$display("\nSet r_Bro = 0, resend packet");
WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
ReceivePacket(16'h0015, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
$display("\n This Broadcast packet will be rejected, r_BRO = 1");
WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
ReceivePacket(16'h0016, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
$display("\n Set r_Bro = 0, resend packet");
WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
WishboneRead({26'h0, `ETH_MODER_ADR}, data_in); // Read from MODER register
WishboneRead({22'h01, (10'h80<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h81<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h83<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h84<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h85<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}, data_in); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}, data_in); // Read from RxBD register
#100000 $stop;
$display("\nEnd TestBroadcast \n");
end
endtask //TestBroadcast
always @ (posedge WB_CLK_I)
begin
if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
begin
repeat(2) @ (posedge WB_CLK_I);
begin
m_wb_ack_i <=#Tp 1'b1;
if(~m_wb_we_o)
begin
#Tp;
if(m_wb_adr_o[1:0] == 2'b00) // word access
begin
m_wb_dat_i[31:24] = memory3[{m_wb_adr_o[31:2], 2'h0}];
m_wb_dat_i[23:16] = memory2[{m_wb_adr_o[31:2], 2'h0}];
m_wb_dat_i[15:08] = memory1[{m_wb_adr_o[31:2], 2'h0}];
m_wb_dat_i[07:00] = memory0[{m_wb_adr_o[31:2], 2'h0}];
end
else if(m_wb_adr_o[1:0] == 2'b10) // half access
begin
m_wb_dat_i[31:24] = 0;
m_wb_dat_i[23:16] = 0;
m_wb_dat_i[15:08] = memory1[{m_wb_adr_o[31:2], 2'h0}];
m_wb_dat_i[07:00] = memory0[{m_wb_adr_o[31:2], 2'h0}];
end
else if(m_wb_adr_o[1:0] == 2'b01) // byte access
begin
m_wb_dat_i[31:24] = 0;
m_wb_dat_i[23:16] = memory2[{m_wb_adr_o[31:2], 2'h0}];
m_wb_dat_i[15:08] = 0;
m_wb_dat_i[07:00] = 0;
end
else if(m_wb_adr_o[1:0] == 2'b11) // byte access
begin
m_wb_dat_i[31:24] = 0;
m_wb_dat_i[23:16] = 0;
m_wb_dat_i[15:08] = 0;
m_wb_dat_i[07:00] = memory0[{m_wb_adr_o[31:2], 2'h0}];
end
$fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
end
else
begin
$fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
if(m_wb_sel_o[0])
memory0[m_wb_adr_o] = m_wb_dat_o[7:0];
if(m_wb_sel_o[1])
memory1[m_wb_adr_o] = m_wb_dat_o[15:8];
if(m_wb_sel_o[2])
memory2[m_wb_adr_o] = m_wb_dat_o[23:16];
if(m_wb_sel_o[3])
memory3[m_wb_adr_o] = m_wb_dat_o[31:24];
end
end
@ (posedge WB_CLK_I);
m_wb_ack_i <=#Tp 1'b0;
end
end
// Detecting ram_oe and ram_we being active at the same time
always @ (posedge WB_CLK_I)
begin
if(tb_eth_top.ethtop.wishbone.ram_we & tb_eth_top.ethtop.wishbone.ram_oe)
begin
$display("\n\n(%0t)ERROR: ram_we and ram_oe both activated at the same time", $time);
#1000;
$stop;
end
end
always @ (posedge WB_CLK_I)
if(tb_eth_top.ethtop.wishbone.RxStatusWrite)
$fdisplay(mcd2, ""); // newline added
task WishboneWrite;
input [31:0] Data;
input [31:0] Address;
integer ii;
begin
wait (~WishboneBusy);
WishboneBusy = 1;
@ (posedge WB_CLK_I);
#1;
WB_ADR_I = Address;
WB_DAT_I = Data;
WB_WE_I = 1'b1;
WB_CYC_I = 1'b1;
WB_STB_I = 1'b1;
WB_SEL_I = 4'hf;
wait(WB_ACK_O); // waiting for acknowledge response
// Writing information about the access to the screen
@ (posedge WB_CLK_I);
if(LogEnable)
begin
if(~Address[11] & ~Address[10])
$write("\n(%0t) Write to register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, Data, Address);
else
if(~Address[11] & Address[10])
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
begin
$write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
if(Address[9:2] == tb_eth_top.ethtop.r_TxBDNum-2'h2)
$write("(%0t) Send Control packet\n", $time);
end
else
$write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
else
$write("\n(%0t) WB write ?????????????? Data: 0x%x Addr: 0x%0x", $time, Data, Address);
end
#1;
WB_ADR_I = 32'hx;
WB_DAT_I = 32'hx;
WB_WE_I = 1'bx;
WB_CYC_I = 1'b0;
WB_STB_I = 1'b0;
WB_SEL_I = 4'hx;
#5 WishboneBusy = 0;
end
endtask
task WishboneRead;
input [31:0] Address;
output[31:0] data;
begin
wait (~WishboneBusy);
WishboneBusy = 1;
@ (posedge WB_CLK_I);
#1;
WB_ADR_I = Address;
WB_WE_I = 1'b0;
WB_CYC_I = 1'b1;
WB_STB_I = 1'b1;
WB_SEL_I = 4'hf;
#3;
wait(WB_ACK_O); // waiting for acknowledge response
@ (posedge WB_CLK_I);
data = WB_DAT_O;
if(~Address[11] & ~Address[10])
// $write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, WB_DAT_O, Address);
$write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, data, Address);
else
if(~Address[11] & Address[10])
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
// ; //$write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
; //$write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, data, Address);
else
// ;//$write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
;//$write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, data, Address);
else
// $write("\n(%0t) WB read ????????? Data: 0x%x Addr: 0x%0x", $time, WB_DAT_O, Address);
$write("\n(%0t) WB read ????????? Data: 0x%x Addr: 0x%0x", $time, data, Address);
#1;
WB_ADR_I = 32'hx;
WB_WE_I = 1'bx;
WB_CYC_I = 1'b0;
WB_STB_I = 1'b0;
WB_SEL_I = 4'hx;
#5 WishboneBusy = 0;
end
endtask
task WishboneReadData;
input [31:0] Address;
output[31:0] data;
begin
@ (posedge WB_CLK_I);
data = {memory3[Address], memory2[Address], memory1[Address], memory0[Address]};
#5;
end
endtask
task WishboneWriteData;
input [31:0] Address;
input [31:0] data;
input [3:0] Select;
begin
@ (posedge WB_CLK_I);
if(Select[0])
memory0[Address] = data[7:0];
if(Select[1])
memory1[Address] = data[15:8];
if(Select[2])
memory2[Address] = data[23:16];
if(Select[3])
memory3[Address] = data[31:24];
// $display("\n(%0t) Write data to memory (Data: 0x%x, Addr: 0x%0x)", $time, data, Address);
#5;
end
endtask
task SendPacket;
input [15:0] Length;
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