?? tb_ethernet.v
字號:
bit_end_2 = 32; // not used
end
endcase
end
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
begin
data = 1'b1 << i_data;
if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
;
else
begin
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
begin
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail("RW bit of the MAC buffer descriptors was not written or not read");
`TIME;
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, addr, data, tmp_data);
end
end
else // data should not be equal to tmp_data
begin
if (tmp_data === data)
begin
fail = fail + 1;
test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
`TIME;
$display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, addr, data, tmp_data);
end
end
end
end
end
// INTERMEDIATE DISPLAYS
case (i)
0: $display(" ->buffer descriptors tested with 0 bus delay");
1: $display(" ->buffer descriptors tested with 1 bus delay cycle");
2: $display(" ->buffer descriptors tested with 2 bus delay cycles");
3: $display(" ->buffer descriptors tested with 3 bus delay cycles");
default: $display(" ->buffer descriptors tested with 4 bus delay cycles");
endcase
end
if(fail == 0)
test_ok;
else
fail = 0;
end
////////////////////////////////////////////////////////////////////
//// ////
//// Test max reg. values and reg. values after writing ////
//// inverse reset values and hard reset of the MAC ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 2) // Start this task
begin
// TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
test_name =
"TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
`TIME; $display(
" TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
// reset MAC registers
hard_reset;
for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
begin
for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
begin
addr = `ETH_BASE + i_addr;
// set ranges of R/W bits
case (addr)
`ETH_MODER:
begin
data = 32'h0000_A800;
data_max = 32'h0001_FFFF;
end
`ETH_INT: // READONLY - tested within INT test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_INT_MASK:
begin
data = 32'h0000_0000;
data_max = 32'h0000_007F;
end
`ETH_IPGT:
begin
data = 32'h0000_0012;
data_max = 32'h0000_007F;
end
`ETH_IPGR1:
begin
data = 32'h0000_000C;
data_max = 32'h0000_007F;
end
`ETH_IPGR2:
begin
data = 32'h0000_0012;
data_max = 32'h0000_007F;
end
`ETH_PACKETLEN:
begin
data = 32'h0040_0600;
data_max = 32'hFFFF_FFFF;
end
`ETH_COLLCONF:
begin
data = 32'h000F_003F;
data_max = 32'h000F_003F;
end
`ETH_TX_BD_NUM:
begin
data = 32'h0000_0040;
data_max = 32'h0000_0080;
end
`ETH_CTRLMODER:
begin
data = 32'h0000_0000;
data_max = 32'h0000_0007;
end
`ETH_MIIMODER:
begin
data = 32'h0000_0064;
data_max = 32'h0000_03FF;
end
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
begin
data = 32'h0000_0000;
data_max = 32'h0000_0007;
end
`ETH_MIIADDRESS:
begin
data = 32'h0000_0000;
data_max = 32'h0000_1F1F;
end
`ETH_MIITX_DATA:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MIISTATUS: // READONLY - tested within MIIM test
begin
data = 32'h0000_0000;
data_max = 32'h0000_0000;
end
`ETH_MAC_ADDR0:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
`ETH_MAC_ADDR1:
begin
data = 32'h0000_0000;
data_max = 32'h0000_FFFF;
end
`ETH_HASH_ADDR0:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
default: // `ETH_HASH_ADDR1:
begin
data = 32'h0000_0000;
data_max = 32'hFFFF_FFFF;
end
endcase
wbm_init_waits = {$random} % 3;
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
if (i == 0)
begin
wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
end
else if (i == 2)
begin
wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
end
else if ((i == 1) || (i == 4))
begin
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail("RESET value of the MAC register is not correct");
`TIME;
$display(" addr %h, data %h, tmp_data %h", addr, data, tmp_data);
end
end
else // check maximum values
begin
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
begin
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail("Previous value of the TX_BD_NUM register did not remain");
`TIME;
$display(" addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
end
// try maximum (80)
wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== data_max)
begin
fail = fail + 1;
test_fail("MAX value of the TX_BD_NUM register is not correct");
`TIME;
$display(" addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
end
// try one less than maximum (80)
wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== (data_max - 1))
begin
fail = fail + 1;
test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
`TIME;
$display(" addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
end
// try one more than maximum (80)
wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== (data_max - 1)) // previous data should remain in this register
begin
fail = fail + 1;
test_fail("Previous value of the TX_BD_NUM register did not remain");
`TIME;
$display(" addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
end
end
else
begin
if (tmp_data !== data_max)
begin
fail = fail + 1;
test_fail("MAX value of the MAC register is not correct");
`TIME;
$display(" addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
end
end
end
end
// reset MAC registers
if ((i == 0) || (i == 3))
hard_reset;
end
if(fail == 0)
test_ok;
else
fail = 0;
end
////////////////////////////////////////////////////////////////////
//// ////
//// Test buffer desc. ram preserving values after hard reset ////
//// of the mac and reseting the logic ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 3) // Start this task
begin
// TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
test_name = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
`TIME;
$display(" TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
// reset MAC registers
hard_reset;
// reset LOGIC with soft reset
// reset_mac;
// reset_mii;
for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
begin
for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
begin
addr = `ETH_BASE + i_addr;
wbm_init_waits = {$random} % 3;
wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
if (i == 0)
begin
data = 32'hFFFFFFFF;
wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
end
else if (i == 2)
begin
data = 32'h00000000;
wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
end
else
begin
wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data !== data)
begin
fail = fail + 1;
test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
`TIME;
$display(" addr %h, data %h, tmp_data %h", addr, data, tmp_data);
end
end
end
if ((i == 0) || (i == 2))
begin
// reset MAC registers
hard_reset;
// reset LOGIC with soft reset
// reset_mac;
// reset_mii;
end
end
if(fail == 0)
test_ok;
else
fail = 0;
end
if (test_num == 4) // Start this task
begin
/* // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
test_name = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
`TIME; $display(" TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
data = 0;
burst_data = 0;
burst_tmp_data = 0;
i_length = 10; // two bursts for length 20
for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
begin
for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
begin
wbm_init_waits = i;
wbm_subseq_waits = i1;
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