?? tb_ethernet.v
字號:
#1;
for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
begin
data = 1'b1 << i_data;
#1;
for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
begin
burst_data = burst_data << 32;
// DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
begin
#1 burst_data[31:0] = 0;
end
else
begin
#1 burst_data[31:0] = data;
end
end
#1;
// 2 burst writes
addr = `ETH_BASE; // address of a first burst
wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
burst_tmp_data = burst_data >> (32 * i_length);
addr = addr + 32'h28; // address of a second burst
wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
#1;
// 2 burst reads
addr = `ETH_BASE; // address of a first burst
wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
wbm_init_waits, wbm_subseq_waits); // first burst
burst_tmp_data = burst_tmp_data << (32 * i_length);
addr = addr + 32'h28; // address of a second burst
wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
wbm_init_waits, wbm_subseq_waits); // second burst
#1;
for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
begin
// set ranges of R/W bits
case (`ETH_BASE + i2)
`ETH_MODER:
begin
bit_start_1 = 0;
bit_end_1 = 16;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_INT: // READONLY - tested within INT test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_INT_MASK:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGT:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGR1:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_IPGR2:
begin
bit_start_1 = 0;
bit_end_1 = 6;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_PACKETLEN:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_COLLCONF:
begin
bit_start_1 = 0;
bit_end_1 = 5;
bit_start_2 = 16;
bit_end_2 = 19;
end
`ETH_TX_BD_NUM:
begin
bit_start_1 = 0;
bit_end_1 = 7;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_CTRLMODER:
begin
bit_start_1 = 0;
bit_end_1 = 2;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIMODER:
begin
bit_start_1 = 0;
bit_end_1 = 9;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIADDRESS:
begin
bit_start_1 = 0;
bit_end_1 = 4;
bit_start_2 = 8;
bit_end_2 = 12;
end
`ETH_MIITX_DATA:
begin
bit_start_1 = 0;
bit_end_1 = 15;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIIRX_DATA: // READONLY - tested within MIIM test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MIISTATUS: // READONLY - tested within MIIM test
begin
bit_start_1 = 32; // not used
bit_end_1 = 32; // not used
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MAC_ADDR0:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_MAC_ADDR1:
begin
bit_start_1 = 0;
bit_end_1 = 15;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
`ETH_HASH_ADDR0:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
default: // `ETH_HASH_ADDR1:
begin
bit_start_1 = 0;
bit_end_1 = 31;
bit_start_2 = 32; // not used
bit_end_2 = 32; // not used
end
endcase
#1;
// 3 LSBits of MIICOMMAND are NOT written !!!
if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
begin
if (burst_tmp_data[31:0] !== burst_data[31:0])
begin
fail = fail + 1;
test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
`TIME;
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
end
end
else
begin
if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
begin
if (burst_tmp_data[31:0] !== burst_data[31:0])
begin
fail = fail + 1;
test_fail("RW bit of the MAC register was not written or not read");
`TIME;
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
end
end
else // data should not be equal to tmp_data
begin
if (burst_tmp_data[31:0] === burst_data[31:0])
begin
fail = fail + 1;
test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
`TIME;
$display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
end
end
end
burst_tmp_data = burst_tmp_data >> 32;
burst_data = burst_data >> 32;
end
end
end
end
if(fail == 0)
test_ok;
else
fail = 0;*/
end
end
end
endtask // test_access_to_mac_reg
task test_mii;
input [31:0] start_task;
input [31:0] end_task;
integer i;
integer i1;
integer i2;
integer i3;
integer cnt;
integer fail;
integer test_num;
reg [8:0] clk_div; // only 8 bits are valid!
reg [4:0] phy_addr;
reg [4:0] reg_addr;
reg [15:0] phy_data;
reg [15:0] tmp_data;
begin
// MIIM MODULE TEST
test_heading("MIIM MODULE TEST");
$display(" ");
$display("MIIM MODULE TEST");
fail = 0;
// reset MAC registers
hard_reset;
// reset MAC and MII LOGIC with soft reset
//reset_mac;
//reset_mii;
//////////////////////////////////////////////////////////////////////
//// ////
//// test_mii: ////
//// ////
//// 0: Test clock divider of mii management module with all ////
//// possible frequences. ////
//// 1: Test various readings from 'real' phy registers. ////
//// 2: Test various writings to 'real' phy registers (control ////
//// and non writable registers) ////
//// 3: Test reset phy through mii management module ////
//// 4: Test 'walking one' across phy address (with and without ////
//// preamble) ////
//// 5: Test 'walking one' across phy's register address (with ////
//// and without preamble) ////
//// 6: Test 'walking one' across phy's data (with and without ////
//// preamble) ////
//// 7: Test reading from phy with wrong phy address (host ////
//// reading high 'z' data) ////
//// 8: Test writing to phy with wrong phy address and reading ////
//// from correct one ////
//// 9: Test sliding stop scan command immediately after read ////
//// request (with and without preamble) ////
//// 10: Test sliding stop scan command immediately after write ////
//// request (with and without preamble) ////
//// 11: Test busy and nvalid status durations during write ////
//// (with and without preamble) ////
//// 12: Test busy and nvalid status durations during write ////
//// (with and without preamble) ////
//// 13: Test busy and nvalid status durations during scan (with ////
//// and without preamble) ////
//// 14: Test scan status from phy with detecting link-fail bit ////
//// (with and without preamble) ////
//// 15: Test scan status from phy with sliding link-fail bit ////
//// (with and without preamble) ////
//// 16: Test sliding stop scan command immediately after scan ////
//// request (with and without preamble) ////
//// 17: Test sliding stop scan command after 2. scan (with and ////
//// without preamble) ////
//// ////
//////////////////////////////////////////////////////////////////////
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
begin
////////////////////////////////////////////////////////////////////
//// ////
//// Test clock divider of mii management module with all ////
//// possible frequences. ////
//// ////
////////////////////////////////////////////////////////////////////
if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
begin
// TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
test_name = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
`TIME; $display(" TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
wait(Mdc_O); // wait for MII clock to be 1
for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
begin
i1 = 0;
i2 = 0;
#Tp mii_set_clk_div(clk_div[7:0]);
@(posedge Mdc_O);
#Tp;
fork
begin
@(posedge Mdc_O);
#Tp;
disable count_i1;
disable count_i2;
end
begin: count_i1
forever
begin
@(posedge wb_clk);
i1 = i1 + 1;
#Tp;
end
end
begin: count_i2
forever
begin
@(negedge wb_clk);
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