/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : Vectors.C
**     Project   : Project
**     Processor : MC9S08DZ60MLF
**     Version   : Bean 01.036, Driver 01.29, CPU db: 2.87.131
**     Compiler  : CodeWarrior HCS08 C Compiler
**     Date/Time : 2008-12-10, 上午 09:28
**     Abstract  :
**         This bean "MC9S08DZ60_48" contains initialization of the
**         CPU and provides basic methods and events for CPU core
**         settings.
**     Settings  :
**
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2006
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : info@processorexpert.com
** ###################################################################*/


#include "Cpu.h"
#include "SM1.h"
extern near void _EntryPoint(void);

void (* near const _vect[])() @0xFFC0 = { /* Interrupt vector table */
         Cpu_Interrupt,                /* Int.no. 31 Vacmp2 (at FFC0)                Unassigned */
         Cpu_Interrupt,                /* Int.no. 30 Vacmp1 (at FFC2)                Unassigned */
         Cpu_Interrupt,                /* Int.no. 29 Vcantx (at FFC4)                Unassigned */
         Cpu_Interrupt,                /* Int.no. 28 Vcanrx (at FFC6)                Unassigned */
         Cpu_Interrupt,                /* Int.no. 27 Vcanerr (at FFC8)               Unassigned */
         Cpu_Interrupt,                /* Int.no. 26 Vcanwu (at FFCA)                Unassigned */
         Cpu_Interrupt,                /* Int.no. 25 Vrtc (at FFCC)                  Unassigned */
         Cpu_Interrupt,                /* Int.no. 24 Viic (at FFCE)                  Unassigned */
         Cpu_Interrupt,                /* Int.no. 23 Vadc (at FFD0)                  Unassigned */
         Cpu_Interrupt,                /* Int.no. 22 Vport (at FFD2)                 Unassigned */
         Cpu_Interrupt,                /* Int.no. 21 Vsci2tx (at FFD4)               Unassigned */
         Cpu_Interrupt,                /* Int.no. 20 Vsci2rx (at FFD6)               Unassigned */
         Cpu_Interrupt,                /* Int.no. 19 Vsci2err (at FFD8)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 18 Vsci1tx (at FFDA)               Unassigned */
         Cpu_Interrupt,                /* Int.no. 17 Vsci1rx (at FFDC)               Unassigned */
         Cpu_Interrupt,                /* Int.no. 16 Vsci1err (at FFDE)              Unassigned */
         SM1_Interrupt,                /* Int.no. 15 Vspi (at FFE0)                  Used */
         Cpu_Interrupt,                /* Int.no. 14 Vtpm2ovf (at FFE2)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 13 Vtpm2ch1 (at FFE4)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 12 Vtpm2ch0 (at FFE6)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 11 Vtpm1ovf (at FFE8)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 10 Vtpm1ch5 (at FFEA)              Unassigned */
         Cpu_Interrupt,                /* Int.no.  9 Vtpm1ch4 (at FFEC)              Unassigned */
         Cpu_Interrupt,                /* Int.no.  8 Vtpm1ch3 (at FFEE)              Unassigned */
         Cpu_Interrupt,                /* Int.no.  7 Vtpm1ch2 (at FFF0)              Unassigned */
         Cpu_Interrupt,                /* Int.no.  6 Vtpm1ch1 (at FFF2)              Unassigned */
         Cpu_Interrupt,                /* Int.no.  5 Vtpm1ch0 (at FFF4)              Unassigned */
         Cpu_Interrupt,                /* Int.no.  4 Vlol (at FFF6)                  Unassigned */
         Cpu_Interrupt,                /* Int.no.  3 Vlvd (at FFF8)                  Unassigned */
         Cpu_Interrupt,                /* Int.no.  2 Virq (at FFFA)                  Unassigned */
         Cpu_Interrupt,                /* Int.no.  1 Vswi (at FFFC)                  Unassigned */
         _EntryPoint                   /* Int.no.  0 Vreset (at FFFE)                Reset vector */
};

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 3.01 [03.92]
**     for the Freescale HCS08 series of microcontrollers.
**
** ###################################################################
*/