?? iir_biquad.asm
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* ======================================================================== *
* TEXAS INSTRUMENTS, INC. *
* *
* NAME *
* iir_biquad -- iir_biquad *
* *
* *
* REVISION DATE *
* 18-May-2005 *
* *
* USAGE *
* *
* This routine is C callable, and has the following C prototype: *
* *
* void iir_biquad *
* ( *
* short * restrict input, *
* int nx, *
* short * restrict output, *
* short * state, *
* short * coeff *
* ); *
* *
* input: Input vector. *
* nx: Number of inputs and outputs. *
* output: Output vector. *
* state: Vector of 4 previous states values. *
* coeff: Vector of 8 Q14 filter coefficients. *
* *
* This routine computes a 2 stage biquad IIR filter. *
* *
* *
* DESCRIPTION *
* *
* The "iir_biquad" fucntion implements a 2 biquad, 2 pole IIR *
* filter for the block of inputs. The poles are between -2 and 1.99. *
* *
* void iir_biquad *
* ( *
* short * restrict input, *
* int nx, *
* short * restrict output, *
* short * state, *
* short * coeff *
* ); *
* { *
* int in, out; *
* int x, t0, t1, p0, p1, p2, p3; *
* short s0, s1, c0, c1, c2, c3; *
* short s2, s3, c4, c5, c6, c7; *
* *
* int i; *
* *
* s0 = state[0]; s1 = state[1]; *
* s2 = state[2]; s3 = state[3]; *
* c0 = coeff[0]; c1 = coeff[1]; *
* c2 = coeff[2]; c3 = coeff[3]; *
* c4 = coeff[4]; c5 = coeff[5]; *
* c6 = coeff[6]; c7 = coeff[7]; *
* *
* for (i=0;i<nx;i++) *
* { *
* in = input[i] << 14; *
* *
* p0 = c2*s0 + c3*s1; *
* p1 = c6*s2 + c7*s3; *
* p2 = c0*s0 + c1*s1; *
* p3 = c4*s2 + c5*s3; *
* t0 = in + p0; *
* x = in + p0 + p2; *
* t1 = x + p1; *
* out = x + p1 + p3; *
* *
* s1 = s0; *
* s0 = t0 >> 14; *
* s3 = s2; *
* s2 = t1 >> 14; *
* *
* output[i] = out >> 14; *
* *
* } *
* *
* state[0] = t0 >> 14; state[1] = s0; *
* state[2] = t1 >> 14; state[3] = s2; *
* *
* } *
* *
* The above C code is a general implementation without *
* restrictions. The assembly code has some restrictions, as *
* noted below. *
* *
* *
* TECHNIQUES *
* *
* The IIR filter has a loop carry dependency of 4 cycles in its *
* intial form. *
* *
* *
* ASSUMPTIONS *
* *
* The input length is greater than or equal to 2. *
* *
* *
* MEMORY NOTE *
* *
* The code is ENDIAN NEUTRAL. *
* *
* *
* CODESIZE *
* *
* 256 bytes *
* *
* *
* CYCLES *
* *
* cycles = count*4 + 25 *
* For count = 16, cycles = 89 *
* *
* ------------------------------------------------------------------------- *
* Copyright (c) 2005 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
* ======================================================================== *
* ======================================================================== *
**********************= SYMBOLIC REGISTER ASSIGNMENTS ************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.map B_state/B19
.map B_state'/B6
.map A_state/A21
.map B_outsh/A3
.map A_x/B4
.map B_c4s2/A3
.map B_c5s3/B17
.map B_c6s2/A16
.map A_c0/B16
.map B_c7s3/B5
.map A_c1/A9
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