LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG IS 
    PORT(D:IN STD_LOGIC_VECTOR(0 TO 7);         //定義一組8個D觸發(fā)器
          CLK:IN STD_LOGIC;
          Q:OUT STD_LOGIC_VECTOR(0 TO 7));
END REG; 
ARCHITECTURE ART OF REG IS
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
           Q<=D;
        END IF;
    END PROCESS;
END ART;