library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity caideng is
port(clk ,clr:in std_logic;
     dout:out std_logic_vector(7 downto 0));
end;
architecture bhv of caideng is
component fenpin
  port( clk,clr: in std_logic;
       clk0,clk1,clk2,clk3,clk4:buffer std_logic);
end  component;
component moore
  port(clk,reset:in std_logic;
       light:out std_logic_vector(7 downto 0));
end  component;
signal clkz:std_logic;
begin
u1: fenpin port map(clk=>clk,clr=>clr,clk4=>clkz);
u2: moore port map(light=>dout,reset=>clr,clk=>clkz);
end bhv;