library ieee;
use ieee.std_logic_1164.all;
entity moore is
port(clk,reset:in std_logic;
light:out std_logic_vector(7 downto 0));
end moore;
architecture bhv of moore is
type st_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16);
signal current_state,next_state:st_type;
begin
reg:process(clk,reset)
begin
if reset='1' then
current_state<=s0;
elsif clk'event and clk='1' then
current_state<=next_state;
end if;
end process;
com:process(current_state,next_state)
begin
case current_state is
when s0=>light<="00000000";
     next_state<=s1;
when s1=>light<="10000000";
     next_state<=s2;
when s2=>light<="01000000";
     next_state<=s3;
when s3=>light<="00100000";
     next_state<=s4;
when s4=>light<="00010000";
     next_state<=s5;
when s5=>light<="00001000";
     next_state<=s6;
when s6=>light<="00000100";
     next_state<=s7;
when s7=>light<="00000010";
     next_state<=s8;
when s8=>light<="00000001";
     next_state<=s9;
when s9=>light<="11111111";
     next_state<=s10;
when s10=>light<="00011000";
     next_state<=s11;
when s11=>light<="00111100";
     next_state<=s12;
when s12=>light<="01111110";
     next_state<=s13;
when s13=>light<="11111111";
     next_state<=s14;
when s14=>light<="01111110";
     next_state<=s15;
when s15=>light<="00111100";
     next_state<=s16;
when s16=>light<="00011000";
     next_state<=s0;
when others=>next_state<=s0;
end case;
end process;
end bhv;