#define	FPGA0				(*((REGP *)(USB_BASE+0x80)))
#define	FPGA1				(*((REGP *)(USB_BASE+0x82)))
#define	FPGA4				(*((REGP *)(USB_BASE+0x88)))
/****************************************/
/*		M66596 Register definition		*/
/****************************************/

/* System Configuration Control Register */
#define	SYSCFG				(*((REGP *)(USB_BASE+0x00)))
#define	XTAL				(0xC000)	/* b15-14: Crystal selection */
#define	  XTAL48			 0x8000		  /* 48MHz */
#define	  XTAL24			 0x4000		  /* 24MHz */
#define	  XTAL12			 0x0000		  /* 12MHz */
#define	XCKE				(0x2000)	/* b13: External clock enable */
#define	RCKE				(0x1000)	/* b12: Register clock enable */
#define	PLLC				(0x0800)	/* b11: PLL control */
#define	SCKE				(0x0400)	/* b10: USB clock enable */
#define	ATCKM				(0x0100)	/* b8: Automatic supply functional enable */
#define	HSE					(0x0080)	/* b7: Hi-speed enable */
#define	DCFM				(0x0040)	/* b6: Controller function select  */
#define	DMRPD				(0x0020)	/* b5: D- pull down control */
#define	DPRPU				(0x0010)	/* b4: D+ pull up control */
#define	FSRPC				(0x0004)	/* b2: Full-speed receiver enable */
#define	PCUT				(0x0002)	/* b1: Low power sleep enable */
#define	USBE				(0x0001)	/* b0: USB module operation enable */

/* System Configuration Status Register */
#define	SYSSTS				(*((REGP *)(USB_BASE+0x02)))
#define	LNST				(0x0003)	/* b1-0: D+, D- line status */
#define	  SE1				 0x0003		  /* SE1 */
#define	  KSTS				 0x0002		  /* K State */
#define	  JSTS				 0x0001		  /* J State */
#define	  SE0				 0x0000		  /* SE0 */

/* Device State Control Register */
#define	DVSTCTR				(*((REGP *)(USB_BASE+0x04)))
#define	WKUP				(0x0100)	/* b8: Remote wakeup */
#define	RWUPE				(0x0080)	/* b7: Remote wakeup sense */
#define	USBRST				(0x0040)	/* b6: USB reset enable */
#define	RESUME				(0x0020)	/* b5: Resume enable */
#define	UACT				(0x0010)	/* b4: USB bus enable */
#define	RHST				(0x0003)	/* b1-0: Reset handshake status */
#define	  HSMODE			 0x0003		  /* Hi-Speed mode */
#define	  FSMODE			 0x0002		  /* Full-Speed mode */
#define	  HSPROC			 0x0001		  /* HS handshake is processing */

/* Test Mode Register */
#define	TESTMODE			(*((REGP *)(USB_BASE+0x06)))
#define	UTST				(0x000F)	/* b4-0: Test select */
#define	  H_TST_PACKET		 0x000C		  /* HOST TEST Packet */
#define	  H_TST_SE0_NAK		 0x000B		  /* HOST TEST SE0 NAK */
#define	  H_TST_K			 0x000A		  /* HOST TEST K */
#define	  H_TST_J			 0x0009		  /* HOST TEST J */
#define	  H_TST_NORMAL		 0x0000		  /* HOST Normal Mode */
#define	  P_TST_PACKET		 0x0004		  /* PERI TEST Packet */
#define	  P_TST_SE0_NAK		 0x0003		  /* PERI TEST SE0 NAK */
#define	  P_TST_K			 0x0002		  /* PERI TEST K */
#define	  P_TST_J			 0x0001		  /* PERI TEST J */
#define	  P_TST_NORMAL		 0x0000		  /* PERI Normal Mode */

/* Data Pin Configuration Register */
#define	PINCFG				(*((REGP *)(USB_BASE+0x0A)))
#define	LDRV				(0x8000)	/* b15: Drive Current Adjust */
#define	BIGEND				(0x0100)	/* b8: Big endian mode */

/* DMAx Pin Configuration Register */
#define	DMA0CFG				(*((REGP *)(USB_BASE+0x0C)))
#define	DMA1CFG				(*((REGP *)(USB_BASE+0x0E)))
#define	DREQA				(0x4000)	/* b14: Dreq active select */
#define	BBURST				(0x2000)	/* b13: Burst mode */
#define	DACKA				(0x0400)	/* b10: Dack active select */
#define	DFORM				(0x0380)	/* b9-7: DMA mode select */
#define	  CPU_ADR_RD_WR		 0x0000		  /* Address + RD/WR mode (CPU bus) */
#define	  CPU_DACK_RD_WR	 0x0100		  /* DACK + RD/WR mode (CPU bus) */
#define	  CPU_DACK_ONLY		 0x0180		  /* DACK only mode (CPU bus) */
#define	  SPLIT_DACK_ONLY	 0x0200		  /* DACK only mode (SPLIT bus) */
#define	  SPLIT_DACK_DSTB	 0x0300		  /* DACK + DSTB0 mode (SPLIT bus) */
#define	DENDA				(0x0040)	/* b6: Dend active select */
#define	PKTM				(0x0020)	/* b5: Packet mode */
#define	DENDE				(0x0010)	/* b4: Dend enable */
#define	OBUS				(0x0004)	/* b2: OUTbus mode */

/* CFIFO/DxFIFO Port Register */
#define	CFIFO				(*((REGP  *)(USB_BASE+0x10)))
#define	CFIFO_8				(*((REGP8 *)(USB_BASE+0x10)))
#define	D0FIFO				(*((REGP  *)(USB_BASE+0x14)))
#define	D0FIFO_8			(*((REGP8 *)(USB_BASE+0x14)))
#define	D1FIFO				(*((REGP  *)(USB_BASE+0x18)))
#define	D1FIFO_8			(*((REGP8 *)(USB_BASE+0x18)))

/* CFIFO/DxFIFO Port Select Register */
#define	CFIFOSEL			(*((REGP *)(USB_BASE+0x1E)))
#define	D0FIFOSEL			(*((REGP *)(USB_BASE+0x24)))
#define	D1FIFOSEL			(*((REGP *)(USB_BASE+0x2A)))
#define	RCNT				(0x8000)	/* b15: Read count mode */
#define	REW					(0x4000)	/* b14: Buffer rewind */
#define	DCLRM				(0x2000)	/* b13: DMA buffer clear mode */
#define	DREQE				(0x1000)	/* b12: DREQ output enable */
#define	MBW					(0x0400)	/* b10: Maximum bit width for FIFO access */
#define	  MBW_8				 0x0000		  /*  8bit */
#define	  MBW_16			 0x0400		  /* 16bit */
#define	TRENB				(0x0200)	/* b9: Transaction counter enable */
#define	TRCLR				(0x0100)	/* b8: Transaction counter clear */
#define	DEZPM				(0x0080)	/* b7: Zero-length packet additional mode */
#define	ISEL				(0x0020)	/* b5: DCP FIFO port direction select */
#define	CURPIPE				(0x0007)	/* b2-0: PIPE select */

/* CFIFO/DxFIFO Port Control Register */
#define	CFIFOCTR			(*((REGP *)(USB_BASE+0x20)))
#define	D0FIFOCTR			(*((REGP *)(USB_BASE+0x26)))
#define	D1FIFOCTR			(*((REGP *)(USB_BASE+0x2C)))
#define	BVAL				(0x8000)	/* b15: Buffer valid flag */
#define	BCLR				(0x4000)	/* b14: Buffer clear */
#define	FRDY				(0x2000)	/* b13: FIFO ready */
#define	DTLN				(0x0FFF)	/* b11-0: FIFO received data length */

/* CFIFO Port SIE Register */
#define	CFIFOSIE			(*((REGP *)(USB_BASE+0x22)))
#define	TGL					(0x8000)	/* b15: Buffer toggle */
#define	SCLR				(0x4000)	/* b14: Buffer clear */
#define	SBUSY				(0x2000)	/* b13: SIE_FIFO busy */

/* DxFIFO Transaction Count Register */
#define	D0FIFOTRN			(*((REGP *)(USB_BASE+0x28)))
#define	D1FIFOTRN			(*((REGP *)(USB_BASE+0x2E)))
#define	TRNCNT				(0xFFFF)	/* b15-0: Transaction counter */

/* Interrupt Enable Register 0 */
#define	INTENB0				(*((REGP *)(USB_BASE+0x30)))
#define	VBSE				(0x8000)	/* b15: VBUS interrupt */
#define	RSME				(0x4000)	/* b14: Resume interrupt */
#define	SOFE				(0x2000)	/* b13: Frame update interrupt */
#define	DVSE				(0x1000)	/* b12: Device state transition interrupt */
#define	CTRE				(0x0800)	/* b11: Control transfer stage transition interrupt */
#define	BEMPE				(0x0400)	/* b10: Buffer empty interrupt */
#define	NRDYE				(0x0200)	/* b9: Buffer not ready interrupt */
#define	BRDYE				(0x0100)	/* b8: Buffer ready interrupt */
#define	URST				(0x0080)	/* b7: USB reset detected interrupt */
#define	SADR				(0x0040)	/* b6: Set address executed interrupt */
#define	SCFG				(0x0020)	/* b5: Set configuration executed interrupt */
#define	SUSP				(0x0010)	/* b4: Suspend detected interrupt */
#define	WDST				(0x0008)	/* b3: Control write data stage completed interrupt */
#define	RDST				(0x0004)	/* b2: Control read data stage completed interrupt */
#define	CMPL				(0x0002)	/* b1: Control transfer complete interrupt */
#define	SERR				(0x0001)	/* b0: Sequence error interrupt */

/* Interrupt Enable Register 1 */
#define	INTENB1				(*((REGP *)(USB_BASE+0x32)))
#define	BCHGE				(0x4000)	/* b14: USB us chenge interrupt */
#define	DTCHE				(0x1000)	/* b12: Detach sense interrupt */
#define	SIGNE				(0x0020)	/* b5: SETUP IGNORE interrupt */
#define	SACKE				(0x0010)	/* b4: SETUP ACK interrupt */
#define	BRDM				(0x0004)	/* b2: BRDY clear timing */
#define	INTL				(0x0002)	/* b1: Interrupt sense select */
#define	PCSE				(0x0001)	/* b0: PCUT enable by CS assert */

/* BRDY Interrupt Enable/Status Register */
#define	BRDYENB				(*((REGP *)(USB_BASE+0x36)))	/* Enable */
#define	BRDYSTS				(*((REGP *)(USB_BASE+0x46)))	/* Status */
#define	BRDY7				(0x0080)	/* b7: PIPE7 */
#define	BRDY6				(0x0040)	/* b6: PIPE6 */
#define	BRDY5				(0x0020)	/* b5: PIPE5 */
#define	BRDY4				(0x0010)	/* b4: PIPE4 */
#define	BRDY3				(0x0008)	/* b3: PIPE3 */
#define	BRDY2				(0x0004)	/* b2: PIPE2 */
#define	BRDY1				(0x0002)	/* b1: PIPE1 */
#define	BRDY0				(0x0001)	/* b1: PIPE0 */

/* NRDY Interrupt Enable/Status Register */
#define	NRDYENB				(*((REGP *)(USB_BASE+0x38)))	/* Enable */
#define	NRDYSTS				(*((REGP *)(USB_BASE+0x48)))	/* Status */
#define	NRDY7				(0x0080)	/* b7: PIPE7 */
#define	NRDY6				(0x0040)	/* b6: PIPE6 */
#define	NRDY5				(0x0020)	/* b5: PIPE5 */
#define	NRDY4				(0x0010)	/* b4: PIPE4 */
#define	NRDY3				(0x0008)	/* b3: PIPE3 */
#define	NRDY2				(0x0004)	/* b2: PIPE2 */
#define	NRDY1				(0x0002)	/* b1: PIPE1 */
#define	NRDY0				(0x0001)	/* b1: PIPE0 */

/* BEMP Interrupt Enable/Status Register */
#define	BEMPENB				(*((REGP *)(USB_BASE+0x3A)))	/* Enable */
#define	BEMPSTS				(*((REGP *)(USB_BASE+0x4A)))	/* Status */
#define	BEMP7				(0x0080)	/* b7: PIPE7 */
#define	BEMP6				(0x0040)	/* b6: PIPE6 */
#define	BEMP5				(0x0020)	/* b5: PIPE5 */
#define	BEMP4				(0x0010)	/* b4: PIPE4 */
#define	BEMP3				(0x0008)	/* b3: PIPE3 */
#define	BEMP2				(0x0004)	/* b2: PIPE2 */
#define	BEMP1				(0x0002)	/* b1: PIPE1 */
#define	BEMP0				(0x0001)	/* b0: PIPE0 */

/* SOF Pin Configuration Register */
#define	SOFCFG				(*((REGP *)(USB_BASE+0x3C)))
#define	SOFM				(0x000C)	/* b3-2: SOF palse mode */
#define	  SOF_125US			 0x0008		  /* SOF OUT 125us uFrame Signal */
#define	  SOF_1MS			 0x0004		  /* SOF OUT 1ms Frame Signal */
#define	  SOF_DISABLE		 0x0000		  /* SOF OUT Disable */

/* Interrupt Status Register 0 */
#define	INTSTS0				(*((REGP *)(USB_BASE+0x40)))
#define	VBINT				(0x8000)	/* b15: VBUS interrupt */
#define	RESM				(0x4000)	/* b14: Resume interrupt */
#define	SOFR				(0x2000)	/* b13: SOF frame update interrupt */
#define	DVST				(0x1000)	/* b12: Device state transition interrupt */
#define	CTRT				(0x0800)	/* b11: Control transfer stage transition interrupt */
#define	BEMP				(0x0400)	/* b10: Buffer empty interrupt */
#define	NRDY				(0x0200)	/* b9: Buffer not ready interrupt */
#define	BRDY				(0x0100)	/* b8: Buffer ready interrupt */
#define	VBSTS				(0x0080)	/* b7: VBUS input port */
#define	DVSQ				(0x0070)	/* b6-4: Device state */
#define	  DS_SPD_CNFG		 0x0070		  /* Suspend Configured */
#define	  DS_SPD_ADDR		 0x0060		  /* Suspend Address */
#define	  DS_SPD_DFLT		 0x0050		  /* Suspend Default */
#define	  DS_SPD_POWR		 0x0040		  /* Suspend Powered */
#define	  DS_SUSP			 0x0040		  /* Suspend */
#define	  DS_CNFG			 0x0030		  /* Configured */
#define	  DS_ADDS			 0x0020		  /* Address */
#define	  DS_DFLT			 0x0010		  /* Default */
#define	  DS_POWR			 0x0000		  /* Powered */
#define	DVSQS				(0x0030)	/* b5-4: Device state */
#define	VALID				(0x0008)	/* b3: Setup packet detected flag */
#define	CTSQ				(0x0007)	/* b2-0: Control transfer stage */
#define	  CS_SQER			 0x0006		  /* Sequence error */
#define	  CS_WRND			 0x0005		  /* Control write nodata status stage */