/*******************************************************************************
COPYRIGHT 2003 STMicroelectronics
Source File Name : st72FLITE3_reg.h
Group            : IPSW,CMG - IPDF
Author           : MCD Application Team
Date First Issued: 23/09/2003
********************************Documentation***********************************
General Purpose - This file contains all the hardware c files for peripherals of
 st72FLITE3.

********************************Revision History********************************
_______________________________________________________________________________
Date :23/09/2003           Release:2.0
      17/05/2004           Release:2.1
                           1.Change all 12 bit registers to extern 
                           2.Removed #pragma 
Date :2/06/2004            Address information added for metrowerks registers                  
____________________________________________________________________________  */


#ifndef ST72fLITE3_REG_H
#define ST72fLITE3_REG_H

#include "ST7lib_config.h"

#ifdef _HIWARE_

/* IO Ports Hardware Registers */
/* Port A Registers */

extern volatile unsigned char PADR @0x00;             /* PORT A data register */ 
extern volatile unsigned char PADDR @0x01;           /*Data direction register*/
extern volatile unsigned char PAOR @0x02;           /* PORT A option register */
/* Port B Registers */
extern volatile unsigned char PBDR @0x03;             /* PORT B data register */          
extern volatile unsigned char PBDDR @0x04;          /*Data direction register */
extern volatile unsigned char PBOR @0x05;           /* PORT B option register */

/* LITE TIMER 2 HARDWARE REGISTERS */
extern volatile unsigned char LTCSR2 @0x08;      /*Control and stats register2*/ 
extern volatile unsigned char LTARR @0x09;            /* Auto-Reload Register */
extern volatile unsigned char LTCNTR @0x0A;               /* Counter Register */
extern volatile unsigned char LTCSR1 @0x0B;     /*Control and stats register 1*/
extern volatile unsigned char LTICR @0x0C;          /* Input capture register */
    
    
/* LART HARDWARE REGISTERS */
extern volatile unsigned char ATCSR @0x0D;       /* Control/Status Register   */
extern volatile unsigned int CNTR   @0x0E;       /* Counter Register 1        */
extern volatile unsigned char CNTR1H @0x0E;       /* Counter Register 1 High  */
extern volatile unsigned char CNTR1L @0x0F;       /* Counter Register 1 Low   */
extern volatile unsigned int ATR1    @0x10;       /* Autoreload Register 1    */
extern volatile unsigned char ATR1H @0x10;       /* Autoreload Register 1 High*/
extern volatile unsigned char ATR1L @0x11;        /* Autoreload Register1 Low */
extern volatile unsigned char PWMCR @0x12;       /* PWM Output control Reg    */
extern volatile unsigned char PWM0CSR @0x13;      /*PWM0 Output control/Status*/ 
extern volatile unsigned char PWM1CSR @0x14;      /*PWM1 Output control/Status*/
extern volatile unsigned char PWM2CSR @0x15;      /*PWM2 Output control/Status*/
extern volatile unsigned char PWM3CSR @0x16;      /*PWM3 Output control/Status*/
extern volatile unsigned int DCR0   @0x17;       /*PWM0 Duty Cycle Register   */
extern volatile unsigned char DCR0H @0x17;       /*PWM0 Duty Cycle HRegister  */
extern volatile unsigned char DCR0L @0x18;       /* PWM Duty Cycle LRegister  */
extern volatile unsigned int DCR1   @0x19;       /*PWM1 Duty Cycle Register   */    
extern volatile unsigned char DCR1H @0x19;      /*PWM 1 Duty Cycle HRegister  */
extern volatile unsigned char DCR1L @0x1A;      /*PWM 1 Duty Cycle LRegister  */
extern volatile unsigned int DCR2   @0x1B;       /*PWM2 Duty Cycle Register   */
extern volatile unsigned char DCR2H @0x1B;      /*PWM 2 Duty Cycle HRegister  */ 
extern volatile unsigned char DCR2L @0x1C;      /*PWM 2 Duty Cycle LRegister  */
extern volatile unsigned int DCR3   @0x1D;       /*PWM3 Duty Cycle Register   */
extern volatile unsigned char DCR3H @0x1D;      /*PWM 3 Duty Cycle HRegister  */ 
extern volatile unsigned char DCR3L @0x1E;      /*PWM 3 Duty Cycle LRegister  */ 
extern volatile unsigned int ATICR @0x1F;        /*Input Capture Register     */
extern volatile unsigned char ATICRH @0x1F;      /*Input Capture Register High*/
extern volatile unsigned char ATICRL @0x20;       /*Input Capture Register Low*/
extern volatile unsigned char ATCSR2 @0x21;      /* Timer Control Register 2  */
extern volatile unsigned char BREAKCR @0x22;        /* Break Control Register */
extern volatile unsigned int ATR2   @0x23;       /*Autoreload Register        */
extern volatile unsigned char ATR2H @0x23;      /* Auto-Reload Register 2 High*/
extern volatile unsigned char ATR2L @0x24;      /* Auto-Reload Register 2 Low */
extern volatile unsigned char DTGR @0x25;       /*Dead Time Generator Register*/
          
/* Watchdog Hardware registers */
extern volatile unsigned char WDGCR @0x2E;       /* Watchdog Control Register */

/* FLASH Hardware Register */
extern volatile unsigned char FCSR @0x2F;     /* Flash Control/Status Register*/
    
/* EEPROM Hardware Registers */  
extern volatile unsigned char EECSR @0x30;     /*EEPROM Control/Stats Register*/

/* SPI HARDWARE REGISTERS */
extern volatile unsigned char SPIDR @0x31;              /* SPI Data register  */
extern volatile unsigned char SPICR @0x32;           /* SPI Control register  */
extern volatile unsigned char SPICSR @0x33;           /* SPI Status register  */
     
/* ADC HARDWARE REGISTERS */
extern volatile unsigned char ADCCSR @0x34;     /*ADC control & stats register*/
extern volatile unsigned char ADCDRH @0x35;      /* Data Register High        */
extern volatile unsigned char ADCDRL @0x36;      /* Data Register Low         */
    
/* ITC HARDWARE RREGISTERS */
extern volatile unsigned char EICR @0x37;       /*External Interrupt Register */ 

/* MCC HARDWARE REGISTERS */
extern volatile unsigned char MCCSR @0x38;     /* MCC Control/Status Register */
    
/* CLK HARDWARE REGISTERS */
extern volatile unsigned char RCCR @0x39;     /*RC Oscillator Control Register*/
extern volatile unsigned char SICSR @0x3A;
                                    /*System Integrity Control/Status register*/
    
/* ITC HARDWARE REGISTERS */
extern volatile unsigned char EISR @0x3C;
                                      /*External Interrupt Selection Register */

/* SCI Hardware Registers */
extern volatile unsigned char SCISR @0x40;                 /* Status Register */
extern volatile unsigned char SCIDR @0x41;                   /* Data Register */
extern volatile unsigned char SCIBRR @0x42;             /* Baud Rate Register */
extern volatile unsigned char SCICR1 @0x43;             /* Control Register 1 */
extern volatile unsigned char SCICR2 @0x44;             /* Control Register 2 */
extern volatile unsigned char SCICR3 @0x45;             /* Control Register 3 */
extern volatile unsigned char SCIERPR @0x46; /*Extended Receive Prescaler Reg */
extern volatile unsigned char SCIETPR @0x47; /*Extended TransmitPrescaler Reg */
           
/* AWU HARDWARE REGISTERS */    
extern volatile unsigned char AWUPR @0x49;           /* AWU Prscaler Register */
extern volatile unsigned char AWUCSR @0x4A;     /*AWU Control/Status Register */

/* DM HARDWARE REGISTERS */
extern volatile unsigned char DMCR @0x4B;              /* DM Control Register */
extern volatile unsigned char DMSR @0x4C;               /* DM Status Register */
extern volatile unsigned char DMBK1H @0x4D;     /*DM Breakpoint register1 High*/
extern volatile unsigned char DMBK1L @0x4E;      /*DM Breakpoint register1 Low*/
extern volatile unsigned char DMBK2H @0x4F;     /*DM Breakpoint register2 High*/          
extern volatile unsigned char DMBK2L @0x50;     /*DM Breakpoint register 2 Low*/
        

#endif /* _HIWARE_ */

/******************************************************************************/
/******************************************************************************/

#ifdef _COSMIC_

/* IO Ports Hardware Registers */
/* Port A Registers */

@tiny volatile unsigned char PADR @0x00;            /* PORT A data register */ 
@tiny volatile unsigned char PADDR @0x01;          /*Data direction register*/
@tiny volatile unsigned char PAOR @0x02;          /* PORT A option register */
/* Port B Registers */
                                                     

@tiny volatile unsigned char PBDR @0x03;            /* PORT B data register */          
@tiny volatile unsigned char PBDDR @0x04;         /*Data direction register */
@tiny volatile unsigned char PBOR @0x05;          /* PORT B option register */

/* LITE TIMER 2 HARDWARE REGISTERS */
@tiny volatile	unsigned char LTCSR2 @0x08;    /*Control and stats register2*/ 
@tiny volatile unsigned char LTARR @0x09;           /* Auto-Reload Register */
@tiny volatile unsigned char LTCNTR @0x0A;              /* Counter Register */
@tiny volatile unsigned char LTCSR1 @0x0B;    /*Control and stats register 1*/
@tiny volatile	unsigned char LTICR @0x0C;        /* Input capture register */
    
    
/* LART HARDWARE REGISTERS */

@tiny volatile	unsigned char ATCSR @0x0D;     /* Control/Status Register   */
@tiny volatile	unsigned int CNTR   @0x0E;     /* Counter Register 1        */
@tiny volatile	unsigned char CNTR1H @0x0E;     /* Counter Register 1 High  */
@tiny volatile	unsigned char CNTR1L @0x0F;     /* Counter Register 1 Low   */
@tiny volatile	unsigned int ATR1    @0x10;     /* Autoreload Register 1    */
@tiny volatile	unsigned char ATR1H @0x10;     /* Autoreload Register 1 High*/
@tiny volatile	unsigned char ATR1L @0x11;      /* Autoreload Register1 Low */
@tiny volatile	unsigned char PWMCR @0x12;     /* PWM Output control Reg    */
@tiny volatile	unsigned char PWM0CSR @0x13;    /*PWM0 Output control/Status*/ 
@tiny volatile	unsigned char PWM1CSR @0x14;    /*PWM1 Output control/Status*/
@tiny volatile	unsigned char PWM2CSR @0x15;    /*PWM2 Output control/Status*/
@tiny volatile	unsigned char PWM3CSR @0x16;    /*PWM3 Output control/Status*/
@tiny volatile	unsigned int DCR0   @0x17;     /*PWM0 Duty Cycle Register   */
@tiny volatile	unsigned char DCR0H @0x17;     /*PWM0 Duty Cycle HRegister  */
@tiny volatile	unsigned char DCR0L @0x18;     /* PWM Duty Cycle LRegister  */
@tiny volatile	unsigned int DCR1   @0x19;     /*PWM1 Duty Cycle Register   */    
@tiny volatile	unsigned char DCR1H @0x19;    /*PWM 1 Duty Cycle HRegister  */
@tiny volatile	unsigned char DCR1L @0x1A;    /*PWM 1 Duty Cycle LRegister  */
@tiny volatile	unsigned int DCR2   @0x1B;     /*PWM2 Duty Cycle Register   */
@tiny volatile	unsigned char DCR2H @0x1B;    /*PWM 2 Duty Cycle HRegister  */ 
@tiny volatile	unsigned char DCR2L @0x1C;    /*PWM 2 Duty Cycle LRegister  */
@tiny volatile	unsigned int DCR3   @0x1D;     /*PWM3 Duty Cycle Register   */
@tiny volatile	unsigned char DCR3H @0x1D;    /*PWM 3 Duty Cycle HRegister  */ 
@tiny volatile	unsigned char DCR3L @0x1E;    /*PWM 3 Duty Cycle LRegister  */ 
@tiny volatile	unsigned int ATICR @0x1F;      /*Input Capture Register     */
@tiny volatile	unsigned char ATICRH @0x1F;    /*Input Capture Register High*/
@tiny volatile	unsigned char ATICRL @0x20;     /*Input Capture Register Low*/
@tiny volatile	unsigned char ATCSR2 @0x21;    /* Timer Control Register 2  */
@tiny volatile	unsigned char BREAKCR @0x22;      /* Break Control Register */
@tiny volatile	unsigned int ATR2   @0x23;     /*Autoreload Register        */
@tiny volatile  unsigned char ATR2H @0x23;    /* Auto-Reload Register 2 High*/
@tiny volatile  unsigned char ATR2L @0x24;    /* Auto-Reload Register 2 Low */
@tiny volatile  unsigned char DTGR @0x25;     /*Dead Time Generator Register*/
          
/* Watchdog Hardware registers */
@tiny volatile unsigned char WDGCR @0x2E;      /* Watchdog Control Register */

/* FLASH Hardware Register */
@tiny volatile unsigned char FCSR @0x2F;    /* Flash Control/Status Register*/
    
/* EEPROM Hardware Registers */  
@tiny volatile unsigned char EECSR @0x30;    /*EEPROM Control/Stats Register*/

/* SPI HARDWARE REGISTERS */

@tiny volatile unsigned char SPIDR @0x31;             /* SPI Data register  */
@tiny volatile unsigned char SPICR @0x32;          /* SPI Control register  */
@tiny volatile unsigned char SPICSR @0x33;          /* SPI Status register  */
     
/* ADC HARDWARE REGISTERS */
@tiny volatile unsigned char ADCCSR @0x34;    /*ADC control & stats register*/
@tiny volatile unsigned char ADCDRH @0x35;     /* Data Register High        */
@tiny volatile unsigned char ADCDRL @0x36;     /* Data Register Low         */
    
/* ITC HARDWARE RREGISTERS */
@tiny volatile unsigned char EICR @0x37;      /*External Interrupt Register */ 

/* MCC HARDWARE REGISTERS */
@tiny volatile unsigned char MCCSR @0x38;    /* MCC Control/Status Register */
    
/* CLK HARDWARE REGISTERS */
@tiny volatile unsigned char RCCR @0x39;    /*RC Oscillator Control Register*/
@tiny volatile unsigned char SICSR @0x3A;
                                    /*System Integrity Control/Status register*/
    
/* ITC HARDWARE REGISTERS */
@tiny volatile unsigned char EISR @0x3C;
                                      /*External Interrupt Selection Register */

/* SCI Hardware Registers */
@tiny volatile unsigned char SCISR @0x40;                /* Status Register */
@tiny volatile unsigned char SCIDR @0x41;                  /* Data Register */
@tiny volatile unsigned char SCIBRR @0x42;            /* Baud Rate Register */
@tiny volatile unsigned char SCICR1 @0x43;            /* Control Register 1 */
@tiny volatile unsigned char SCICR2 @0x44;            /* Control Register 2 */
@tiny volatile unsigned char SCICR3 @0x45;            /* Control Register 3 */
@tiny volatile unsigned char SCIERPR @0x46;/*Extended Receive Prescaler Reg */
@tiny volatile unsigned char SCIETPR @0x47;/*Extended TransmitPrescaler Reg */
           
/* AWU HARDWARE REGISTERS */    
@tiny volatile unsigned char AWUPR @0x49;          /* AWU Prscaler Register */
@tiny volatile unsigned char AWUCSR @0x4A;    /*AWU Control/Status Register */

/* DM HARDWARE REGISTERS */
@tiny volatile unsigned char DMCR @0x4B;             /* DM Control Register */
@tiny volatile unsigned char DMSR @0x4C;              /* DM Status Register */
@tiny volatile unsigned char DMBK1H @0x4D;    /*DM Breakpoint register1 High*/
@tiny volatile unsigned char DMBK1L @0x4E;     /*DM Breakpoint register1 Low*/
@tiny volatile unsigned char DMBK2H @0x4F;    /*DM Breakpoint register2 High*/          
@tiny volatile unsigned char DMBK2L @0x50;    /*DM Breakpoint register 2 Low*/
    
#endif /* _COSMIC_ */    
#endif /* ST72fLITE3 */