?? idea_en_top.vhd
字號:
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--
-- Library Name : Idea_vhd_100M
-- Unit Name : EN_KEY_GEN
-- Unit Type : Block Diagram
--
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library ieee;use ieee.STD_LOGIC_1164.all;use ieee.NUMERIC_STD.all;entity EN_KEY_GEN is port ( KEY_IN : in std_logic_vector(127 downto 0 ); ZY_BUS_1 : out std_logic_vector(95 downto 0 ); ZY_BUS_2 : out std_logic_vector(95 downto 0 ); ZY_BUS_3 : out std_logic_vector(95 downto 0 ); ZY_BUS_4 : out std_logic_vector(95 downto 0 ); ZY_BUS_5 : out std_logic_vector(95 downto 0 ); ZY_BUS_6 : out std_logic_vector(95 downto 0 ); ZY_BUS_7 : out std_logic_vector(95 downto 0 ); ZY_BUS_8 : out std_logic_vector(95 downto 0 ); ZY_BUS_9 : out std_logic_vector(63 downto 0 ) ); end EN_KEY_GEN; architecture EN_KEY_GEN of EN_KEY_GEN is signal S10 : std_logic_vector(1 downto 0 ); signal S11 : std_logic_vector(4 downto 0 ); signal S12 : std_logic_vector(10 downto 0 ); signal S13 : std_logic_vector(11 downto 0 ); signal S14 : std_logic_vector(3 downto 0 ); signal S16 : std_logic_vector(12 downto 0 ); signal S17 : std_logic_vector(2 downto 0 ); signal S7 : std_logic_vector(8 downto 0 ); signal S8 : std_logic_vector(6 downto 0 ); signal S9 : std_logic_vector(13 downto 0 ); signal Z1 : std_logic_vector(15 downto 0 ); signal Z10 : std_logic_vector(15 downto 0 ); signal Z11 : std_logic_vector(15 downto 0 ); signal Z12 : std_logic_vector(15 downto 0 ); signal Z13 : std_logic_vector(15 downto 0 ); signal Z14 : std_logic_vector(15 downto 0 ); signal Z15 : std_logic_vector(15 downto 0 ); signal Z16 : std_logic_vector(15 downto 0 ); signal Z17 : std_logic_vector(15 downto 0 ); signal Z18 : std_logic_vector(15 downto 0 ); signal Z19 : std_logic_vector(15 downto 0 ); signal Z2 : std_logic_vector(15 downto 0 ); signal Z20 : std_logic_vector(15 downto 0 ); signal Z21 : std_logic_vector(15 downto 0 ); signal Z22 : std_logic_vector(15 downto 0 ); signal Z23 : std_logic_vector(15 downto 0 ); signal Z24 : std_logic_vector(15 downto 0 ); signal Z25 : std_logic_vector(15 downto 0 ); signal Z26 : std_logic_vector(15 downto 0 ); signal Z27 : std_logic_vector(15 downto 0 ); signal Z28 : std_logic_vector(15 downto 0 ); signal Z29 : std_logic_vector(15 downto 0 ); signal Z3 : std_logic_vector(15 downto 0 ); signal Z30 : std_logic_vector(15 downto 0 ); signal Z31 : std_logic_vector(15 downto 0 ); signal Z32 : std_logic_vector(15 downto 0 ); signal Z33 : std_logic_vector(15 downto 0 ); signal Z34 : std_logic_vector(15 downto 0 ); signal Z35 : std_logic_vector(15 downto 0 ); signal Z36 : std_logic_vector(15 downto 0 ); signal Z37 : std_logic_vector(15 downto 0 ); signal Z38 : std_logic_vector(15 downto 0 ); signal Z39 : std_logic_vector(15 downto 0 ); signal Z4 : std_logic_vector(15 downto 0 ); signal Z40 : std_logic_vector(15 downto 0 ); signal Z41 : std_logic_vector(15 downto 0 ); signal Z42 : std_logic_vector(15 downto 0 ); signal Z43 : std_logic_vector(15 downto 0 ); signal Z44 : std_logic_vector(15 downto 0 ); signal Z45 : std_logic_vector(15 downto 0 ); signal Z46 : std_logic_vector(15 downto 0 ); signal Z47 : std_logic_vector(15 downto 0 ); signal Z48 : std_logic_vector(15 downto 0 ); signal Z49 : std_logic_vector(15 downto 0 ); signal Z5 : std_logic_vector(15 downto 0 ); signal Z50 : std_logic_vector(15 downto 0 ); signal Z51 : std_logic_vector(15 downto 0 ); signal Z52 : std_logic_vector(15 downto 0 ); signal Z6 : std_logic_vector(15 downto 0 ); signal Z7 : std_logic_vector(15 downto 0 ); signal Z8 : std_logic_vector(15 downto 0 ); signal Z9 : std_logic_vector(15 downto 0 ); begin Z8(15 downto 0) <= KEY_IN(15 downto 0); Z7(15 downto 0) <= KEY_IN(31 downto 16); Z6(15 downto 0) <= KEY_IN(47 downto 32); Z5(15 downto 0) <= KEY_IN(63 downto 48); Z4(15 downto 0) <= KEY_IN(79 downto 64); Z3(15 downto 0) <= KEY_IN(95 downto 80); Z2(15 downto 0) <= KEY_IN(111 downto 96); Z1(15 downto 0) <= KEY_IN(127 downto 112); Z16(15 downto 0) <= KEY_IN(118 downto 103); Z13(15 downto 0) <= KEY_IN(38 downto 23); Z12(15 downto 0) <= KEY_IN(54 downto 39); Z11(15 downto 0) <= KEY_IN(70 downto 55); Z14(15 downto 0) <= KEY_IN(22 downto 7); Z10(15 downto 0) <= KEY_IN(86 downto 71); Z9(15 downto 0) <= KEY_IN(102 downto 87); S7(8 downto 0) <= KEY_IN(127 downto 119); S8(6 downto 0) <= KEY_IN(6 downto 0); Z15(15 downto 9) <= S8(6 downto 0); Z15(8 downto 0) <= S7(8 downto 0); Z24(15 downto 0) <= KEY_IN(93 downto 78); Z20(15 downto 0) <= KEY_IN(29 downto 14); Z19(15 downto 0) <= KEY_IN(45 downto 30); Z18(15 downto 0) <= KEY_IN(61 downto 46); Z17(15 downto 0) <= KEY_IN(77 downto 62); Z23(15 downto 0) <= KEY_IN(109 downto 94); Z22(15 downto 0) <= KEY_IN(125 downto 110); S9(13 downto 0) <= KEY_IN(13 downto 0); S10(1 downto 0) <= KEY_IN(127 downto 126); Z21(15 downto 2) <= S9(13 downto 0); Z21(1 downto 0) <= S10(1 downto 0); Z29(15 downto 0) <= KEY_IN(116 downto 101); S12(10 downto 0) <= KEY_IN(127 downto 117); S11(4 downto 0) <= KEY_IN(4 downto 0); Z31(15 downto 0) <= KEY_IN(84 downto 69); Z30(15 downto 0) <= KEY_IN(100 downto 85); Z27(15 downto 0) <= KEY_IN(20 downto 5); Z26(15 downto 0) <= KEY_IN(36 downto 21); Z32(15 downto 0) <= KEY_IN(68 downto 53); Z25(15 downto 0) <= KEY_IN(52 downto 37); Z28(15 downto 11) <= S11(4 downto 0); Z28(10 downto 0) <= S12(10 downto 0); Z40(15 downto 0) <= KEY_IN(43 downto 28); Z39(15 downto 0) <= KEY_IN(59 downto 44); Z38(15 downto 0) <= KEY_IN(75 downto 60); Z37(15 downto 0) <= KEY_IN(91 downto 76); Z36(15 downto 0) <= KEY_IN(107 downto 92); Z35(15 downto 0) <= KEY_IN(123 downto 108); S14(3 downto 0) <= KEY_IN(127 downto 124); S13(11 downto 0) <= KEY_IN(11 downto 0); Z33(15 downto 0) <= KEY_IN(27 downto 12); Z34(15 downto 4) <= S13(11 downto 0); Z34(3 downto 0) <= S14(3 downto 0); Z48(15 downto 0) <= KEY_IN(18 downto 3); Z47(15 downto 0) <= KEY_IN(34 downto 19); Z46(15 downto 0) <= KEY_IN(50 downto 35); Z45(15 downto 0) <= KEY_IN(66 downto 51); Z44(15 downto 0) <= KEY_IN(82 downto 67); Z43(15 downto 0) <= KEY_IN(98 downto 83); Z42(15 downto 0) <= KEY_IN(114 downto 99); S16(12 downto 0) <= KEY_IN(127 downto 115); S17(2 downto 0) <= KEY_IN(2 downto 0); Z41(15 downto 13) <= S17(2 downto 0); Z41(12 downto 0) <= S16(12 downto 0); Z52(15 downto 0) <= KEY_IN(57 downto 42); Z51(15 downto 0) <= KEY_IN(73 downto 58); Z50(15 downto 0) <= KEY_IN(89 downto 74); Z49(15 downto 0) <= KEY_IN(105 downto 90); ZY_BUS_1(95 downto 80) <= Z1(15 downto 0); ZY_BUS_1(79 downto 64) <= Z2(15 downto 0); ZY_BUS_1(63 downto 48) <= Z3(15 downto 0); ZY_BUS_1(47 downto 32) <= Z4(15 downto 0); ZY_BUS_1(31 downto 16) <= Z5(15 downto 0); ZY_BUS_1(15 downto 0) <= Z6(15 downto 0); ZY_BUS_5(95 downto 80) <= Z25(15 downto 0); ZY_BUS_5(79 downto 64) <= Z26(15 downto 0); ZY_BUS_5(63 downto 48) <= Z27(15 downto 0); ZY_BUS_5(47 downto 32) <= Z28(15 downto 0); ZY_BUS_5(31 downto 16) <= Z29(15 downto 0); ZY_BUS_5(15 downto 0) <= Z30(15 downto 0); ZY_BUS_2(95 downto 80) <= Z7(15 downto 0); ZY_BUS_2(79 downto 64) <= Z8(15 downto 0); ZY_BUS_2(63 downto 48) <= Z9(15 downto 0); ZY_BUS_2(47 downto 32) <= Z10(15 downto 0); ZY_BUS_2(31 downto 16) <= Z11(15 downto 0); ZY_BUS_2(15 downto 0) <= Z12(15 downto 0); ZY_BUS_6(95 downto 80) <= Z31(15 downto 0); ZY_BUS_6(79 downto 64) <= Z32(15 downto 0); ZY_BUS_6(63 downto 48) <= Z33(15 downto 0); ZY_BUS_6(47 downto 32) <= Z34(15 downto 0); ZY_BUS_6(31 downto 16) <= Z35(15 downto 0); ZY_BUS_6(15 downto 0) <= Z36(15 downto 0); ZY_BUS_3(95 downto 80) <= Z13(15 downto 0); ZY_BUS_3(79 downto 64) <= Z14(15 downto 0); ZY_BUS_3(63 downto 48) <= Z15(15 downto 0); ZY_BUS_3(47 downto 32) <= Z16(15 downto 0); ZY_BUS_3(31 downto 16) <= Z17(15 downto 0); ZY_BUS_3(15 downto 0) <= Z18(15 downto 0); ZY_BUS_7(95 downto 80) <= Z37(15 downto 0); ZY_BUS_7(79 downto 64) <= Z38(15 downto 0); ZY_BUS_7(63 downto 48) <= Z39(15 downto 0); ZY_BUS_7(47 downto 32) <= Z40(15 downto 0); ZY_BUS_7(31 downto 16) <= Z41(15 downto 0); ZY_BUS_7(15 downto 0) <= Z42(15 downto 0); ZY_BUS_4(95 downto 80) <= Z19(15 downto 0); ZY_BUS_4(79 downto 64) <= Z20(15 downto 0); ZY_BUS_4(63 downto 48) <= Z21(15 downto 0); ZY_BUS_4(47 downto 32) <= Z22(15 downto 0); ZY_BUS_4(31 downto 16) <= Z23(15 downto 0); ZY_BUS_4(15 downto 0) <= Z24(15 downto 0); ZY_BUS_8(95 downto 80) <= Z43(15 downto 0); ZY_BUS_8(79 downto 64) <= Z44(15 downto 0); ZY_BUS_8(63 downto 48) <= Z45(15 downto 0); ZY_BUS_8(47 downto 32) <= Z46(15 downto 0); ZY_BUS_8(31 downto 16) <= Z47(15 downto 0); ZY_BUS_8(15 downto 0) <= Z48(15 downto 0); ZY_BUS_9(63 downto 48) <= Z49(15 downto 0); ZY_BUS_9(47 downto 32) <= Z50(15 downto 0); ZY_BUS_9(31 downto 16) <= Z51(15 downto 0); ZY_BUS_9(15 downto 0) <= Z52(15 downto 0);end EN_KEY_GEN;----------------------------------------------------
--
-- Library Name : Idea_vhd_100M
-- Unit Name : ED_64_L_CT
-- Unit Type : State Machine
--
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library ieee;use ieee.STD_LOGIC_1164.all;use ieee.STD_LOGIC_UNSIGNED.all;use ieee.STD_LOGIC_ARITH.all;use ieee.STD_LOGIC_MISC.all;entity ED_64_L_CT is port ( CLK : in std_logic; RST : in std_logic; ZY_CTRL : out std_logic_vector(3 downto 0 ); CTRL : out std_logic_vector(1 downto 0 ); OV : out std_logic; ZO : in std_logic; BUSY : out std_logic; E_RUS : out std_logic ); end ED_64_L_CT; architecture ED_64_L_CT of ED_64_L_CT is type visual_S0_states is (S0, S12, S14, S15, S17, S2, S3, S4, S5, S6, S7); signal visual_S0_current : visual_S0_states; begin -- Synchronous process ED_64_L_CT_S0: process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then ZY_CTRL<="0000"; CTRL<="00"; OV<='0'; BUSY<='0'; E_RUS<='0'; visual_S0_current <= S0; elsif (RST = '0') then ZY_CTRL<="0000"; CTRL<="00"; OV<='0'; BUSY<='0'; E_RUS<='0'; visual_S0_current <= S0; else case visual_S0_current is when S0 => if (ZO = '1') then BUSY<='1'; ZY_CTRL<="0000"; CTRL<="00"; visual_S0_current <= S14; else visual_S0_current <= S0; end if; when S12 => ZY_CTRL<="0010"; visual_S0_current <= S2; when S14 => ZY_CTRL<="0001"; CTRL<="01"; visual_S0_current <= S12; when S15 => OV<='1'; E_RUS<='0'; visual_S0_current <= S17; when S17 => ZY_CTRL<="0000"; CTRL<="00"; OV<='0'; BUSY<='0'; E_RUS<='0'; visual_S0_current <= S0; when S2 => ZY_CTRL<="0011"; visual_S0_current <= S3; when S3 => ZY_CTRL<="0100"; visual_S0_current <= S4; when S4 => ZY_CTRL<="0101"; visual_S0_current <= S5; when S5 => ZY_CTRL<="0110"; visual_S0_current <= S6; when S6 => ZY_CTRL<="0111"; visual_S0_current <= S7; when S7 => ZY_CTRL<="1000"; CTRL<="10"; E_RUS<='1'; visual_S0_current <= S15; when others => ZY_CTRL<="0000"; CTRL<="00"; OV<='0'; BUSY<='0'; E_RUS<='0'; visual_S0_current <= S0; end case; end if; end if; end process; end ED_64_L_CT;----------------------------------------------------
--
-- Library Name : Idea_vhd_100M
-- Unit Name : MADD_16
-- Unit Type : Block Diagram
--
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library ieee;use ieee.STD_LOGIC_1164.all;use ieee.STD_LOGIC_ARITH.all;use ieee.STD_LOGIC_UNSIGNED.all;entity MADD_16 is port ( A : in std_logic_vector(15 downto 0 ); B : in std_logic_vector(15 downto 0 ); O : out std_logic_vector(15 downto 0 ) ); end MADD_16; architecture MADD_16 of MADD_16 is signal visual_C0_sum_int : std_logic_vector(16 downto 0 ); signal visual_C0_tmp_a : std_logic_vector(16 - 1 downto 0 ); signal visual_C0_tmp_b : std_logic_vector(16 - 1 downto 0 ); constant visual_C0_zero : std_logic_vector(16 - 1 downto 0 ) := (others => '0'); begin ?? 快捷鍵說明
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