SET_FLAG DEBUG FALSE
SET_FLAG MODE INTERACTIVE
SET_FLAG STANDALONE_MODE TRUE
SET_PREFERENCE flowvendor Foundation_ISE
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim true
SET_PREFERENCE subworkingdirectory ./tmp/_cg
SET_PREFERENCE workingdirectory ./tmp/
SET_PREFERENCE speedgrade -1
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE asysymbol true
SET_PREFERENCE addpads false
SET_PREFERENCE outputdirectory ./
SET_PREFERENCE device xc5vsx95t
SET_PREFERENCE projectname coregen
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE foundationsym false
SET_PREFERENCE package ff1136
SET_PREFERENCE createndf false
SET_PREFERENCE designentry VHDL
SET_PREFERENCE devicefamily virtex5
SET_PREFERENCE formalverification false
SET_PREFERENCE removerpms false
SET_SIM_PARAMETER c_a_type 1
SET_SIM_PARAMETER c_ccm_imp 0
SET_SIM_PARAMETER c_round_output 0
SET_SIM_PARAMETER c_b_type 0
SET_SIM_PARAMETER c_out_low 0
SET_SIM_PARAMETER c_latency 3
SET_SIM_PARAMETER c_b_value 10000001
SET_SIM_PARAMETER c_has_sclr 0
SET_SIM_PARAMETER c_mult_type 0
SET_SIM_PARAMETER c_has_ce 0
SET_SIM_PARAMETER component_name mul_sweep
SET_SIM_PARAMETER c_ce_overrides_sclr 0
SET_SIM_PARAMETER c_optimize_goal 1
SET_SIM_PARAMETER c_round_pt 0
SET_SIM_PARAMETER c_b_width 24
SET_SIM_PARAMETER c_a_width 24
SET_SIM_PARAMETER c_out_high 47
SET_SIM_PARAMETER c_has_zero_detect 0
SET_PARAMETER portbtype Signed
SET_PARAMETER clockenable false
SET_PARAMETER multtype Parallel_Multiplier
SET_PARAMETER ccmimp Distributed_Memory
SET_PARAMETER constvalue 129
SET_PARAMETER roundpoint 0
SET_PARAMETER outputwidthhigh 47
SET_PARAMETER use_custom_output_width false
SET_PARAMETER component_name mul_sweep
SET_PARAMETER pipestages 3
SET_PARAMETER userounding false
SET_PARAMETER zerodetect false
SET_PARAMETER optgoal Speed
SET_PARAMETER portawidth 24
SET_PARAMETER multiplier_construction Use_LUTs
SET_PARAMETER outputwidthlow 0
SET_PARAMETER sclrcepriority SCLR_Overrides_CE
SET_PARAMETER portatype Unsigned
SET_PARAMETER portbwidth 24
SET_PARAMETER syncclear false
SET_PARAMETER internaluser 0
SET_CORE_CLASS com.xilinx.ip.mult_gen_v11_2.mult_gen_v11_2
SET_CORE_PATH d:\Xilinx\12.4\ISE_DS\ISE\coregen\ip\xilinx\dsp\com\xilinx\ip\mult_gen_v11_2\
SET_CORE_NAME Multiplier
SET_CORE_VERSION 11.2
SET_CORE_DATASHEET d:\Xilinx\12.4\ISE_DS\ISE\coregen\ip\xilinx\dsp\com\xilinx\ip\mult_gen_v11_2\doc\mult_gen_ds255.pdf