----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  MADD16_IN
--  Unit    Type :  Block Diagram
--  
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 library ieee;use ieee.STD_LOGIC_1164.all;use ieee.STD_LOGIC_UNSIGNED.all;use ieee.STD_LOGIC_ARITH.all;entity MADD16_IN is  port (        D : in std_logic_vector(15 downto 0 );        Q : out std_logic_vector(15 downto 0 )        );  end MADD16_IN;  architecture MADD16_IN of MADD16_IN is   signal O : std_logic_vector(15 downto 0 );  signal S2 : std_logic_vector(15 downto 0 );  signal S3 : std_logic_vector(15 downto 0 );  signal visual_C4_dif_int : std_logic_vector(16 downto 0 );  signal visual_C4_tmp_a : std_logic_vector(16 - 1 downto 0 );  signal visual_C4_tmp_b : std_logic_vector(16 - 1 downto 0 );  constant visual_C4_zero : std_logic_vector(16 - 1 downto 0 ) := (others  =>                                                  '0');  signal visual_C6_sum_int : std_logic_vector(16 downto 0 );  signal visual_C6_tmp_a : std_logic_vector(16 - 1 downto 0 );  signal visual_C6_tmp_b : std_logic_vector(16 - 1 downto 0 );  constant visual_C6_zero : std_logic_vector(16 - 1 downto 0 ) := (others  =>                                                  '0');  begin   O(15 downto 0) <= "1111111111111111";       visual_C4_tmp_a <= (O(15 downto 0));    visual_C4_tmp_b <= (D(15 downto 0));    visual_C4_dif_int <= (unsigned('0' & visual_C4_tmp_a)       - unsigned('0' & visual_C4_tmp_b));        S2(15 downto 0) <= (visual_C4_dif_int(16 - 1 downto 0));       visual_C6_tmp_a <= (S2(15 downto 0));    visual_C6_tmp_b <= (S3(15 downto 0));    visual_C6_sum_int <= (unsigned('0' & visual_C6_tmp_a)       + unsigned('0' & visual_C6_tmp_b));        Q(15 downto 0) <= (visual_C6_sum_int(16 - 1 downto 0));    S3(15 downto 0) <= "0000000000000001"; end MADD16_IN;----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  ADD_17_ST
--  Unit    Type :  Block Diagram
--  
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 library ieee;use ieee.STD_LOGIC_1164.all;use ieee.STD_LOGIC_ARITH.all;use ieee.STD_LOGIC_UNSIGNED.all;entity ADD_17_ST is  port (        A1 : in std_logic_vector(16 downto 0 );        A2 : in std_logic_vector(16 downto 0 );        CO_N1N2 : in std_logic;        OV : out std_logic;        OV1 : in std_logic;        OV2 : in std_logic;        Q : out std_logic_vector(16 downto 0 )        );  end ADD_17_ST;  architecture ADD_17_ST of ADD_17_ST is   signal CI_1 : std_logic;  signal CO_GT : std_logic;  signal CO_GT0 : std_logic;  signal CTRL_1 : std_logic;  signal CTRL_2 : std_logic_vector(2 downto 0 );  signal I1 : std_logic;  signal I2 : std_logic;  signal I3 : std_logic;  signal I4 : std_logic;  signal I5 : std_logic;  signal I6 : std_logic;  signal I7 : std_logic;  signal I8 : std_logic;  signal O1 : std_logic_vector(16 downto 0 );  signal O2 : std_logic_vector(16 downto 0 );  signal S : std_logic_vector(1 downto 0 );  signal S51 : std_logic_vector(16 downto 0 );  signal S56 : std_logic_vector(16 downto 0 );  signal visual_C0_sum_int : std_logic_vector(17 downto 0 );  signal visual_C0_tmp_a : std_logic_vector(17 - 1 downto 0 );  signal visual_C0_tmp_b : std_logic_vector(17 - 1 downto 0 );  constant visual_C0_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>                                                  '0');  signal visual_C1_dif_int : std_logic_vector(17 downto 0 );  signal visual_C1_tmp_a : std_logic_vector(17 - 1 downto 0 );  signal visual_C1_tmp_b : std_logic_vector(17 - 1 downto 0 );  constant visual_C1_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>                                                  '0');  signal visual_C24_O : std_logic;  signal visual_C36_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C40_O : std_logic;  begin      visual_C0_tmp_a <= (A1(16 downto 0));    visual_C0_tmp_b <= (A2(16 downto 0));    visual_C0_sum_int <= (unsigned('0' & visual_C0_tmp_a)       + unsigned('0' & visual_C0_tmp_b));        S51(16 downto 0) <= (visual_C0_sum_int(17 - 1 downto 0));       visual_C1_tmp_a <= (A2(16 downto 0));    visual_C1_tmp_b <= (A1(16 downto 0));    visual_C1_dif_int <= (unsigned('0' & visual_C1_tmp_a)       - unsigned('0' & visual_C1_tmp_b)) - unsigned(visual_C1_zero & (CI_1));        S56(16 downto 0) <= (visual_C1_dif_int(17 - 1 downto 0));        CO_GT0 <= (visual_C1_dif_int(17));   CTRL_2(2) <= OV1;  CTRL_2(1) <= OV2;  CTRL_2(0) <= CO_GT;   OV <= (visual_C24_O);   process (I1 , I2 , I3 , I4 , I5 , I6 , I7 , I8 , CTRL_2)   begin     case CTRL_2(2 downto 0) is       when "000" =>         visual_C24_O <=  I1;       when "001" =>         visual_C24_O <=  I2;       when "010" =>         visual_C24_O <=  I3;       when "011" =>         visual_C24_O <=  I4;       when "100" =>         visual_C24_O <=  I5;       when "101" =>         visual_C24_O <=  I6;       when "110" =>         visual_C24_O <=  I7;       when others =>         visual_C24_O <=  I8;     end case;   end process;    I1 <= '0';    I2 <= '1';    I3 <= '0';    I4 <= '0';    I5 <= '1';    I6 <= '1';    I7 <= '1';    I8 <= '0';     CTRL_1 <= ( OV1) xor ( OV2);    Q(16 downto 0) <= (visual_C36_O);   process (S56 , O2 , S51 , S)   begin     case S(1 downto 0) is       when "00" =>         visual_C36_O <=  S56(16 downto 0);       when "01" =>         visual_C36_O <=  O2(16 downto 0);       when "10" =>         visual_C36_O <=  S51(16 downto 0);       when others =>         visual_C36_O <=  S51(16 downto 0);     end case;   end process;    S(1) <= CTRL_1;  S(0) <= CO_GT0;   O1(16 downto 0) <= not (S56(16 downto 0));    O2(16 downto 0) <= (unsigned((O1(16 downto 0))) + 1);    CI_1 <= '0';    CO_GT <= (visual_C40_O);   process (CO_GT0 , CO_N1N2)   begin     case CO_N1N2 is       when '0' =>         visual_C40_O <=  CO_GT0;       when others =>         visual_C40_O <= not CO_GT0;     end case;   end process; end ADD_17_ST;----------------------------------------------------
--  
--  Library Name :  Idea_vhd_100M
--  Unit    Name :  MMUL_16A1_IN_2
--  Unit    Type :  Block Diagram
--  
------------------------------------------------------
 library ieee;use ieee.STD_LOGIC_1164.all;use ieee.STD_LOGIC_ARITH.all;use ieee.STD_LOGIC_UNSIGNED.all;entity MMUL_16A1_IN_2 is  port (        A1 : in std_logic_vector(16 downto 0 );        A1_1 : out std_logic_vector(16 downto 0 );        A2 : in std_logic_vector(16 downto 0 );        N1 : in std_logic_vector(16 downto 0 );        N2 : in std_logic_vector(16 downto 0 );        N2_1 : out std_logic_vector(16 downto 0 );        OV : out std_logic;        OV1 : in std_logic;        OV2 : in std_logic;        OV_1 : out std_logic;        OV_2 : out std_logic;        Q : out std_logic_vector(15 downto 0 );        A2_1 : out std_logic_vector(16 downto 0 );        N1_1 : out std_logic_vector(16 downto 0 )        );  end MMUL_16A1_IN_2;  use work.all;architecture MMUL_16A1_IN_2 of MMUL_16A1_IN_2 is   signal CO_N1N2 : std_logic;  signal I1 : std_logic_vector(16 downto 0 );  signal OV3 : std_logic;  signal OV_20 : std_logic;  signal S10 : std_logic_vector(16 downto 0 );  signal S11 : std_logic_vector(16 downto 0 );  signal S12 : std_logic_vector(16 downto 0 );  signal S121 : std_logic_vector(16 downto 0 );  signal S134 : std_logic;  signal S158 : std_logic;  signal S161 : std_logic;  signal S180 : std_logic_vector(16 downto 0 );  signal S19 : std_logic_vector(16 downto 0 );  signal S2 : std_logic_vector(16 downto 0 );  signal S26 : std_logic_vector(16 downto 0 );  signal S27 : std_logic;  signal S28 : std_logic;  signal S30 : std_logic_vector(16 downto 0 );  signal S35 : std_logic_vector(1 downto 0 );  signal S38 : std_logic;  signal S40 : std_logic_vector(16 downto 0 );  signal S41 : std_logic_vector(16 downto 0 );  signal S42 : std_logic_vector(16 downto 0 );  signal S6 : std_logic_vector(16 downto 0 );  signal S61 : std_logic_vector(16 downto 0 );  signal S7 : std_logic_vector(16 downto 0 );  signal SY : std_logic;  signal SY1 : std_logic;  signal TJ1 : std_logic;  signal TJ3 : std_logic;  component ADD_17_ST      port (            A1 : in std_logic_vector(16 downto 0 );            A2 : in std_logic_vector(16 downto 0 );            CO_N1N2 : in std_logic;            OV : out std_logic;            OV1 : in std_logic;            OV2 : in std_logic;            Q : out std_logic_vector(16 downto 0 )            );  end component;  signal visual_C1_dif_int : std_logic_vector(17 downto 0 );  signal visual_C1_tmp_a : std_logic_vector(17 - 1 downto 0 );  signal visual_C1_tmp_b : std_logic_vector(17 - 1 downto 0 );  constant visual_C1_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>                                                  '0');  signal visual_C13_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C16_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C17_O : std_logic;  signal visual_C18_O : std_logic;  signal visual_C92_O : std_logic;  signal visual_C20_O : std_logic;  signal visual_C147_dif_int : std_logic_vector(17 downto 0 );  signal visual_C147_tmp_a : std_logic_vector(17 - 1 downto 0 );  signal visual_C147_tmp_b : std_logic_vector(17 - 1 downto 0 );  constant visual_C147_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>                                                  '0');  signal visual_C29_O : std_logic_vector(16 - 1 downto 0 );  signal visual_C142_dif_int : std_logic_vector(17 downto 0 );  signal visual_C142_tmp_a : std_logic_vector(17 - 1 downto 0 );  signal visual_C142_tmp_b : std_logic_vector(17 - 1 downto 0 );  constant visual_C142_zero : std_logic_vector(17 - 1 downto 0 ) := (others  =>                                                  '0');  signal visual_C145_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C12_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C31_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C32_O : std_logic_vector(17 - 1 downto 0 );  signal visual_C24_O : std_logic;  signal visual_C27_O : std_logic;   -- Start Configuration Specification  -- ++ for all : ADD_17_ST use entity work.ADD_17_ST(ADD_17_ST);  -- End Configuration Specification begin  OV_2 <= OV_20;  A2_1 <= S26(16 downto 0);  N1_1 <= S7(16 downto 0);   C103: ADD_17_ST    port map (              A1 => A2(16 downto 0),              A2 => A1(16 downto 0),              CO_N1N2 => CO_N1N2,              OV => OV3,              OV1 => S27,              OV2 => S28,              Q => I1(16 downto 0)              );      visual_C142_tmp_a <= (N1(16 downto 0));    visual_C142_tmp_b <= (N2(16 downto 0));    visual_C142_dif_int <= (unsigned('0' & visual_C142_tmp_a)       - unsigned('0' & visual_C142_tmp_b)) - unsigned(visual_C142_zero & (S134));        S40(16 downto 0) <= (visual_C142_dif_int(17 - 1 downto 0));        CO_N1N2 <= (visual_C142_dif_int(17));   S2(16 downto 0) <= (visual_C145_O);   process (S42 , S40 , CO_N1N2)   begin     case CO_N1N2 is       when '1' =>         visual_C145_O <=  S42(16 downto 0);       when others =>         visual_C145_O <=  S40(16 downto 0);     end case;   end process;    S6(16) <= S134;  S6(15 downto 0) <= N1(16 downto 1);   TJ1 <= not (N1(0));   TJ3 <= not (A1(0));   S134 <= '0';    S7(16 downto 0) <= (visual_C12_O);   process (S2 , S6 , TJ1)   begin     case TJ1 is       when '0' =>         visual_C12_O <=  S2(16 downto 0);       when others =>         visual_C12_O <=  S6(16 downto 0);     end case;   end process;    N2_1(16 downto 0) <= (visual_C31_O);   process (N1 , N2 , SY)   begin     case SY is       when '0' =>         visual_C31_O <=  N1(16 downto 0);       when others =>         visual_C31_O <=  N2(16 downto 0);     end case;   end process;    S26(16 downto 0) <= (visual_C32_O);   process (A1 , A2 , SY)   begin     case SY is       when '0' =>         visual_C32_O <=  A1(16 downto 0);       when others =>         visual_C32_O <=  A2(16 downto 0);     end case;   end process;    OV_20 <= (visual_C24_O);   process (OV1 , OV2 , SY)   begin     case SY is       when '0' =>         visual_C24_O <=  OV1;       when others =>         visual_C24_O <=  OV2;     end case;   end process;    S41(16 downto 0) <= not (S40(16 downto 0));    S42(16 downto 0) <= (unsigned((S41(16 downto 0))) + 1);    SY <= (visual_C27_O);   process (CO_N1N2 , TJ1 , SY1)   begin     case SY1 is       when '0' =>         visual_C27_O <= not CO_N1N2;       when others =>         visual_C27_O <=  TJ1;     end case;   end process;     SY1 <= ( TJ1) or ( CO_N1N2);     process (S7 , S61)   begin      if ((S7(16 downto 0)) = (S61(16 downto 0))) then        OV <= '1';      else        OV <= '0';      end if;  end process;    S61(16 downto 0) <= "00000000000000000";       visual_C1_tmp_a <= (S30(16 downto 0));    visual_C1_tmp_b <= (A1(16 downto 0));    visual_C1_dif_int <= (unsigned('0' & visual_C1_tmp_a)       - unsigned('0' & visual_C1_tmp_b));        S10(16 downto 0) <= (visual_C1_dif_int(17 - 1 downto 0));    S11(16) <= S134;  S11(15 downto 0) <= S10(16 downto 1);   S12(16) <= S134;  S12(15 downto 0) <= A1(16 downto 1);   S19(16 downto 0) <= (visual_C13_O);   process (S11 , S12 , TJ3)   begin     case TJ3 is       when '0' =>         visual_C13_O <=  S11(16 downto 0);       when others =>         visual_C13_O <=  S12(16 downto 0);     end case;   end process;