?? idea_de_top.vhd
字號:
begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C1_Q <= (others => '0'); else if (E1 = '1') then visual_C1_Q <= (Y37(15 downto 0)); end if; end if; end if; end process; Y22(15 downto 0) <= (visual_C3_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C3_Q <= (others => '0'); else if (E1 = '1') then visual_C3_Q <= (Y25(15 downto 0)); end if; end if; end if; end process; Y10(15 downto 0) <= (visual_C4_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C4_Q <= (others => '0'); else if (E1 = '1') then visual_C4_Q <= (Y13(15 downto 0)); end if; end if; end if; end process; Y43(15 downto 0) <= (visual_C5_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C5_Q <= (others => '0'); else if (E1 = '1') then visual_C5_Q <= (Y46(15 downto 0)); end if; end if; end if; end process; Y31(15 downto 0) <= (visual_C6_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C6_Q <= (others => '0'); else if (E1 = '1') then visual_C6_Q <= (Y34(15 downto 0)); end if; end if; end if; end process; Y19(15 downto 0) <= (visual_C7_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C7_Q <= (others => '0'); else if (E1 = '1') then visual_C7_Q <= (Y22(15 downto 0)); end if; end if; end if; end process; Y7(15 downto 0) <= (visual_C9_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C9_Q <= (others => '0'); else if (E1 = '1') then visual_C9_Q <= (Y10(15 downto 0)); end if; end if; end if; end process; Y40(15 downto 0) <= (visual_C10_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C10_Q <= (others => '0'); else if (E1 = '1') then visual_C10_Q <= (Y43(15 downto 0)); end if; end if; end if; end process; Y28(15 downto 0) <= (visual_C11_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C11_Q <= (others => '0'); else if (E1 = '1') then visual_C11_Q <= (Y31(15 downto 0)); end if; end if; end if; end process; Y16(15 downto 0) <= (visual_C12_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C12_Q <= (others => '0'); else if (E1 = '1') then visual_C12_Q <= (Y19(15 downto 0)); end if; end if; end if; end process; Y4(15 downto 0) <= (visual_C13_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C13_Q <= (others => '0'); else if (E1 = '1') then visual_C13_Q <= (Y7(15 downto 0)); end if; end if; end if; end process; Y37(15 downto 0) <= (visual_C14_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C14_Q <= (others => '0'); else if (E1 = '1') then visual_C14_Q <= (Y40(15 downto 0)); end if; end if; end if; end process; Y25(15 downto 0) <= (visual_C15_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C15_Q <= (others => '0'); else if (E1 = '1') then visual_C15_Q <= (Y28(15 downto 0)); end if; end if; end if; end process; Y13(15 downto 0) <= (visual_C16_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C16_Q <= (others => '0'); else if (E1 = '1') then visual_C16_Q <= (Y16(15 downto 0)); end if; end if; end if; end process; Y1(15 downto 0) <= (visual_C17_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C17_Q <= (others => '0'); else if (E1 = '1') then visual_C17_Q <= (Y4(15 downto 0)); end if; end if; end if; end process; Y50(15 downto 0) <= (visual_C124_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C124_Q <= (others => '0'); else if (E1 = '1') then visual_C124_Q <= (Y51(15 downto 0)); end if; end if; end if; end process; Y51(15 downto 0) <= (visual_C125_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C125_Q <= (others => '0'); else if (E1 = '1') then visual_C125_Q <= (MADD16OUT1(15 downto 0)); end if; end if; end if; end process; MADD16_1(15 downto 0) <= (visual_C24_O); process (Z50 , Z51 , Z45 , Z44 , Z39 , Z38 , Z33 , Z32 , Z27 , Z26 , Z21 , Z20 , Z15 , Z14 , Z9 , Z8 , DEK_SEL) begin case DEK_SEL(3 downto 0) is when "0000" => visual_C24_O <= Z50(15 downto 0); when "0001" => visual_C24_O <= Z51(15 downto 0); when "0010" => visual_C24_O <= Z45(15 downto 0); when "0011" => visual_C24_O <= Z44(15 downto 0); when "0100" => visual_C24_O <= Z39(15 downto 0); when "0101" => visual_C24_O <= Z38(15 downto 0); when "0110" => visual_C24_O <= Z33(15 downto 0); when "0111" => visual_C24_O <= Z32(15 downto 0); when "1000" => visual_C24_O <= Z27(15 downto 0); when "1001" => visual_C24_O <= Z26(15 downto 0); when "1010" => visual_C24_O <= Z21(15 downto 0); when "1011" => visual_C24_O <= Z20(15 downto 0); when "1100" => visual_C24_O <= Z15(15 downto 0); when "1101" => visual_C24_O <= Z14(15 downto 0); when "1110" => visual_C24_O <= Z9(15 downto 0); when others => visual_C24_O <= Z8(15 downto 0); end case; end process; MADD2_1(15 downto 0) <= (visual_C33_O); process (Z2 , Z3 , DEK_SEL) begin case DEK_SEL(0) is when '0' => visual_C33_O <= Z2(15 downto 0); when others => visual_C33_O <= Z3(15 downto 0); end case; end process; MADD18_1(15 downto 0) <= (visual_C34_O); process (MADD16_1 , MADD2_1 , DEK_SEL) begin case DEK_SEL(4) is when '0' => visual_C34_O <= MADD16_1(15 downto 0); when others => visual_C34_O <= MADD2_1(15 downto 0); end case; end process; Y45(15 downto 0) <= (visual_C108_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C108_Q <= (others => '0'); else if (E1 = '1') then visual_C108_Q <= (Y50(15 downto 0)); end if; end if; end if; end process; Y33(15 downto 0) <= (visual_C109_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C109_Q <= (others => '0'); else if (E1 = '1') then visual_C109_Q <= (Y38(15 downto 0)); end if; end if; end if; end process; Y21(15 downto 0) <= (visual_C111_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C111_Q <= (others => '0'); else if (E1 = '1') then visual_C111_Q <= (Y26(15 downto 0)); end if; end if; end if; end process; Y9(15 downto 0) <= (visual_C112_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C112_Q <= (others => '0'); else if (E1 = '1') then visual_C112_Q <= (Y14(15 downto 0)); end if; end if; end if; end process; Y44(15 downto 0) <= (visual_C113_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C113_Q <= (others => '0'); else if (E1 = '1') then visual_C113_Q <= (Y45(15 downto 0)); end if; end if; end if; end process; Y32(15 downto 0) <= (visual_C114_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C114_Q <= (others => '0'); else if (E1 = '1') then visual_C114_Q <= (Y33(15 downto 0)); end if; end if; end if; end process; Y20(15 downto 0) <= (visual_C115_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C115_Q <= (others => '0'); else if (E1 = '1') then visual_C115_Q <= (Y21(15 downto 0)); end if; end if; end if; end process; Y8(15 downto 0) <= (visual_C116_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C116_Q <= (others => '0'); else if (E1 = '1') then visual_C116_Q <= (Y9(15 downto 0)); end if; end if; end if; end process; Y39(15 downto 0) <= (visual_C106_Q); process (CLK) begin if (CLK'event and CLK = '1') then if (RST = '0') then visual_C106_Q <= (others => '0'); else if (E1 = '1') then visual_C106_Q <= (Y44(15 downto 0)); end if; end if; end if; end process; Y27(15 downto 0) <= (visual_C107_Q); process (CLK
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